Phase-locked loop circuit, data recovery circuit, and control method for phase-locked loop circuit

Patent metadata

Field	Value
Publication number	US-9654115-B2
Application number	US-201615268120-A
Country	US
Kind code	B2
Filing date	Sep 16, 2016
Priority date	Sep 16, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A phase-locked loop circuit, which includes a phase frequency detector, a charge pump, a loop low-pass filter, a first voltage-current converter, a second voltage-current converter, a current-controlled oscillator, a frequency divider, a comparator, and a mode controller, where the mode controller is configured to control the switches S 1, S 2, and S 3 included in the loop low-pass filter to connect or disconnect. Using the phase-locked loop circuit, a voltage value of a second control voltage signal VC 2 provided for the first voltage-current converter can reach, in a relatively short time, a voltage value of a first control voltage signal VC 1 provided for the second voltage-current converter, thereby increasing a speed of establishing the phase-locked loop circuit and implementing a quick response of the phase-locked loop circuit.

First claim

What is claimed is:

1. A phase-locked loop circuit, comprising:
a first voltage-current converter;
a second voltage-current converter;
a current-controlled oscillator;
a frequency divider;
a phase frequency detector configured to:
receive a reference source signal and a feedback signal that is output by the frequency divider; and
generate a first error signal;

a charge pump coupled to the phase frequency detector and configured to generate a first voltage signal according to the first error signal that is output by the phase frequency detector;
a loop low-pass filter, comprising a first filter, a second filter, a third node, and a fourth node, a switch (S 1 ), a switch (S 2 ), and a switch (S 3 ), wherein the first filter is configured to filter out a high frequency component in the first voltage signal that is output by the charge pump and generate a first control voltage signal (VC 1 ) to provide for the second voltage-current converter, wherein the second filter is configured to filter out the high frequency component in the first voltage signal that is output by the charge pump and generate a second control voltage signal (VC 2 ) to provide for the first voltage-current converter, wherein the first filter comprises a first resistor (R 1 ) and a first capacitor (C 1 ), wherein the R 1 and the C 1 are connected in series, wherein the second filter comprises a second resistor (R 2 ) and a second capacitor (C 2 ), wherein the R 2 and the C 2 are connected in series, wherein the third node is a node for taking out the VC 1 , wherein the fourth node is another node for taking out the VC 2 , wherein a first end of the S 1 is coupled to a first node between the R 1 and the C 1 , wherein a second end of the S 1 is coupled to a second node between the R 2 and the C 2 , wherein two ends of the S 2 are respectively coupled to the first node and the fourth node, and wherein two ends of the S 3 are respectively coupled to the third node and the fourth node; and
a mode controller coupled to the loop low-pass filter and configured to control the S 1 to alternatively connect and disconnect, the S 2 to connect, and the S 3 to disconnect in the loop low-pass filter when a bandwidth of the phase-locked loop circuit is less than a bandwidth threshold,
wherein the first voltage-current converter is coupled to the loop low-pass filter and configured to:
convert the received VC 2 into a current signal; and
input the current signal to the current-controlled oscillator;

wherein the second voltage-current converter is coupled to the loop low-pass filter and configured to:
convert the received VC 1 into another current signal; and
input the other current signal to the current-controlled oscillator,

wherein the current-controlled oscillator is configured to generate, according to received current signals, a phase-locked loop output signal whose frequency is a target frequency,
wherein one end of the frequency divider is coupled to the current-controlled oscillator and the other end is coupled to the phase frequency detector, and
wherein the frequency divider is configured to:
perform frequency division on the frequency of the phase-locked loop output signal that is output by the current-controlled oscillator;
set a signal that is obtained after the frequency division as a frequency division feedback signal; and
send the frequency division feedback signal to the phase frequency detector.

2. The phase-locked loop circuit according to claim 1 , further comprising a comparator coupled to the first node, the second node, and the mode controller and configured to:
receive a voltage VM 1 at the first node and a voltage VM 2 at the second node;
determine an output signal according to a differential mode voltage between the VM 1 and the VM 2 ; and
send the output signal to the mode controller, and
wherein the mode controller is further configured to control, according to the output signal of the comparator, the S 1 to alternatively connect and disconnect.

3. The phase-locked loop circuit according to claim 2 , wherein the comparator is further configured to:
compare a first voltage threshold with a value of the differential mode voltage between the VM 1 and the VM 2 ; and
generate a first level signal as the output signal when the value of the differential mode voltage between the VM 1 and the VM 2 is greater than the first voltage threshold;
send the first level signal to the mode controller when the value of the differential mode voltage between the VM 1 and the VM 2 is greater than the first voltage threshold;
generate a second level signal as the output signal when the value of the differential mode voltage between the VM 1 and the VM 2 is not greater than the first voltage threshold; and
send the second level signal to the mode controller when the value of the differential mode voltage between the VM 1 and the VM 2 is not greater than the first voltage threshold, and
wherein the mode controller is further configured to:
control the S 1 to connect when receiving the first level signal; and
control the S 1 to disconnect when receiving the second level signal.

4. The phase-locked loop circuit according to claim 3 , wherein the comparator comprises:
a selector;
a first comparator;
a common-mode voltage (VCM) generator configured to:
receive the voltage VM 1 at the first node and the voltage VM 2 at the second node; and
generate a VCM of the VM 1 and the VM 2 ; and

a determining component connected to the selector and the VCM generator and configured to:
compare a second voltage threshold with the VCM generated by the VCM generator;
output a first instruction signal to the selector when the VCM is less than the second voltage threshold; and
output a second instruction signal to the selector when the VCM is greater than the second voltage threshold,

wherein the selector is configured to:
receive the first instruction signal that is output by the determining component;
select to receive, according to the first instruction signal, a first output signal that is generated by the first comparator; and
set the first output signal as the output signal of the comparator, and

wherein the first comparator is configured to generate the first level signal as the first output signal when the VCM of the voltage VM 1 at the first node and the voltage VM 2 at the second node is less than the second voltage threshold.

5. The phase-locked loop circuit according to claim 3 , wherein the comparator comprises:
a selector;
a first comparator;
a common-mode voltage (VCM) generator configured to:
receive the voltage VM 1 at the first node and the voltage VM 2 at the second node; and
generate a VCM of the VM 1 and the VM 2 ; and

a determining component connected to the selector and the VCM generator and configured to:
compare a second voltage threshold with the VCM generated by the VCM generator;
output a first instruction signal to the selector when the VCM is less than the second voltage threshold; and
output a second instruction signal to the selector when the VCM is greater than the second voltage threshold,

wherein the selector is configured to:
receive the first instruction signal that is output by the determining component;
select to receive, according to the first instruction signal, a first output signal that is generated by the first comparator; and
set the first output signal as the output signal of the comparator, and

wherein the first comparator is configured to generate the second level signal as the first output signal when the VCM of the voltage VM 1 at the first node and the voltage VM 2 at the second node is less than the second voltage threshold.

6. The phase-locked loop circuit according to cla

Assignees

• Huawei Tech Co Ltd

Inventors

• Zhang Bingzhao
• Liu Yongwang

Classifications

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/1075 Primary

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title