Power semiconductor device

US12308305B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12308305-B2
Application numberUS-201917754779-A
CountryUS
Kind codeB2
Filing dateNov 28, 2019
Priority dateNov 28, 2019
Publication dateMay 20, 2025
Grant dateMay 20, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An object of the present invention is to provide a power semiconductor device enabling a downsizing of a module. A power semiconductor device according to the present invention includes: emitter main electrodes each provided in each of a plurality of semiconductor chips; and main electrode emitter sense terminals directly connected to each of the emitter main electrodes and partially exposed outside a module, wherein each of the main electrode emitter sense terminals is located diagonally to each other, and a distance from each of the main electrode emitter sense terminals to each of the emitter main electrodes connected to each of the main electrode emitter sense terminals is smaller than a distance between the main electrode emitter sense terminals in a plan view outside the module.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power semiconductor device, comprising: main electrodes each connected to corresponding ones of a plurality of semiconductor chips; main electrode emitter sense terminals each directly connected to a corresponding one of the main electrodes and partially exposed outside a module; and auxiliary emitter sense terminals indirectly connected to each of the main electrodes and partially exposed outside the module, wherein each of the main electrode emitter sense terminals is located diagonally to each other, and a distance from each of the main electrode emitter sense terminals to each of the main electrodes connected to each of the main electrode emitter sense terminals is smaller than a distance between the main electrode emitter sense terminals in a plan view outside the module, and each of the auxiliary emitter sense terminals is located diagonally to each other. 2. The power semiconductor device according to claim 1 , wherein each of the auxiliary emitter sense terminals is located opposite to the main electrode emitter sense terminals in a plan view outside the module. 3. The power semiconductor device according to claim 1 , wherein each of the main electrode emitter sense terminals is a cylindrical nut, and is connected to each of the main electrodes by swaging. 4. The power semiconductor device according to claim 1 , wherein each of the main electrode emitter sense terminals is a cylindrical nut, and is connected to each of the main electrodes with a screw. 5. The power semiconductor device according to claim 1 , wherein each of the main electrode emitter sense terminals includes a cylindrical nut, a lead wiring connected to the cylindrical nut, and a connector connected to the lead wiring, and the connector is connected to each of the main electrodes. 6. The power semiconductor device according to claim 1 , wherein each of the main electrode emitter sense terminals includes a cylindrical nut and an insert wiring connected to the cylindrical nut, and the insert wiring is connected to each of the main electrodes. 7. The power semiconductor device according to claim 1 , wherein each of the main electrode emitter sense terminals is an insert wiring connected to each of the main electrodes. 8. The power semiconductor device according to claim 1 , wherein each of the main electrode emitter sense terminals is a spring contact pin provided inside a cover of the module. 9. The power semiconductor device according to claim 8 , wherein the main electrodes and the spring contact pin are covered with a sealing agent. 10. The power semiconductor device according to claim 1 , wherein each of the semiconductor chips is made up of a wide bandgap semiconductor material. 11. The power semiconductor device according to claim 1 , wherein each of the main electrode emitter sense terminals is bent inside the module. 12. A power semiconductor device, comprising: main electrodes each connected to a corresponding one of a plurality of semiconductor chips; and main electrode emitter sense terminals each directly connected to a corresponding one of the main electrodes and partially exposed outside a module, wherein each of the main electrode emitter sense terminals is located diagonally to each other, and a distance from each of the main electrode emitter sense terminals to each of the main electrodes connected to each of the main electrode emitter sense terminals is smaller than a distance between the main electrode emitter sense terminals in a plan view outside the module, and each of the main electrode emitter sense terminals is a cylindrical nut, and is connected to each of the main electrodes by swaging. 13. A power semiconductor device, comprising: main electrodes each connected to a corresponding one of a plurality of semiconductor chips; and main electrode emitter sense terminals each directly connected to a corresponding one of the main electrodes and partially exposed outside a module, wherein each of the main electrode emitter sense terminals is located diagonally to each other, and a distance from each of the main electrode emitter sense terminals to each of the main electrodes connected to each of the main electrode emitter sense terminals is smaller than a distance between the main electrode emitter sense terminals in a plan view outside the module, and each of the main electrode emitter sense terminals is an insert wiring connected to each of the main electrodes.

Assignees

Inventors

Classifications

  • Encapsulations, e.g. protective coatings · CPC title

  • Die-attach connectors and bond wires · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • H10W90/701Primary

    characterised by the relative positions of pads or connectors relative to package parts · CPC title

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Frequently asked questions

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What does patent US12308305B2 cover?
An object of the present invention is to provide a power semiconductor device enabling a downsizing of a module. A power semiconductor device according to the present invention includes: emitter main electrodes each provided in each of a plurality of semiconductor chips; and main electrode emitter sense terminals directly connected to each of the emitter main electrodes and partially exposed ou…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 20 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).