Method for obtaining parameters of semiconductor structure, method for obtaining detection standard and detection method

Patent metadata

Field	Value
Publication number	US-12308295-B2
Application number	US-202117504587-A
Country	US
Kind code	B2
Filing date	Oct 19, 2021
Priority date	Jan 25, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Embodiments of the present disclosure provide a method for obtaining parameters of a semiconductor structure, a method for obtaining a detection standard and a detection method. The method for obtaining parameters of a semiconductor structure includes: obtaining a semiconductor structure, the semiconductor structure including a substrate and a capacitor support structure on the substrate, the capacitor support structure having a plurality of capacitor holes therein, the capacitor holes penetrating the capacitor support structure in a thickness direction of the capacitor support structure; removing some height of the capacitor support structure; obtaining a test pattern, the test pattern being a pattern exposed at a top of the remaining capacitor support structure; and in the test pattern, obtaining a spacing between the capacitor holes at predetermined positions on the basis of a predetermined direction.

First claim

What is claimed is:

1. A method for obtaining parameters of a semiconductor structure, comprising:
obtaining a semiconductor structure, the semiconductor structure comprising a substrate and a capacitor support structure on the substrate, the capacitor support structure having a plurality of capacitor holes therein, the capacitor holes penetrating the capacitor support structure in a thickness direction of the capacitor support structure;
removing the capacitor support structure with partial height;
obtaining a test pattern, the test pattern being a pattern exposed at a top of the remaining capacitor support structure; and
determining a measurement interval in the test pattern, wherein the measurement interval comprising the capacitor holes in M rows and N columns, M and N being natural numbers greater than or equal to 2;
obtaining a plurality of spacings in a predetermined direction, wherein each spacing is a distance between the capacitor holes at predetermined positions in the measurement interval;
obtaining an offset range according to maximum and minimum ones of the plurality of spacings in a single row/column in the predetermined direction, the offset range indicating a distance between the maximum and minimum ones of the plurality of spacings; and
obtaining an offset distance, wherein the offset distance is an average of the plurality of offset ranges.

2. The method for obtaining parameters of a semiconductor structure according to claim 1 , before the removing the capacitor support structure with the partial height, further comprising
the following step:
forming a protective layer on sidewalls of the capacitor hole.

3. The method for obtaining parameters of a semiconductor structure according to claim 2 , wherein
the step of the forming the protective layer on sidewalls of the capacitor hole comprises:
forming a protective film covering both a top surface of the capacitor support structure and the sidewalls of the capacitor hole; and
removing the protective film on the surface of the capacitor support structure to form the protective layer on the sidewalls of the capacitor hole.

4. The method for obtaining parameters of a semiconductor structure according to claim 1 , wherein
during removing the capacitor support structure with the partial height, the method further comprises:
obtaining a dimensional variation of the plurality of capacitor holes in the pattern exposed at the top of the capacitor support structure, the dimensional variation being used to represent a value of a dimensional change in the plurality of capacitor holes in the process of removing the capacitor support structure with the partial height.

5. The method for obtaining parameters of a semiconductor structure according to claim 4 , wherein
the step of the obtaining the dimensional variation of the plurality of capacitor holes in the pattern exposed at the top of the capacitor support structure comprises:
according to a dimension of each capacitor hole in the semiconductor structure, obtaining a maximum value of a dimensional change in each capacitor hole in the process of removing the capacitor support structure with the partial height; and
according to the maximum value of the dimensional change in the capacitor hole, obtaining the dimensional variation,
wherein the dimensional variation is an average of the multiple maximum values of the dimension change in the capacitor holes.

6. A method for obtaining a detection standard, according to the method for obtaining parameters of the semiconductor structure according to claim 1 , further comprising:
obtaining a yield of a products corresponding to the semiconductor structure; and
obtaining a first test relationship between the partial height which is a height of the capacitor support structure removed from the semiconductor structure and the offset distance under the yield.

7. The method for obtaining a detection standard according to claim 6 , further comprising:
obtaining a plurality of yields of products corresponding to different semiconductor structures, and obtaining the first test relationship under different yields; and
according to the first test relationship under different yields, establishing a second test relationship among the partial height, the offset distance, and the yield.

8. The method for obtaining a detection standard according to claim 6 , wherein
during removing the capacitor support structure with the partial height, the method further comprises:
obtaining a dimensional variation of the plurality of capacitor holes in the pattern exposed at the top of the capacitor support structure, the dimensional variation being used to represent a value of a dimensional change in the capacitor hole in the process of removing the capacitor support structure with the partial height; and
obtaining a third test relationship between the partial height and the dimensional variation under the yield.

9. The method for obtaining a detection standard according to claim 8 , comprising:
obtaining a plurality of yields of products corresponding to different semiconductor structures, and obtaining the third test relationship under different yields; and
according to the third test relationship under different yields, establishing a fourth test relationship among the partial height, the dimensional variation, and the yield.

10. The method for obtaining parameters of a semiconductor structure according to claim 1 , wherein,
the predetermined direction refers to a direction of the row;
or,
the predetermined direction refers to a direction of the column;
or,
the predetermined direction refers to a direction of the row and a direction of the column.

11. The method for obtaining parameters of a semiconductor structure according to claim 1 , wherein,
the distance between the capacitor holes at predetermined positions refers to a distance between adjacent capacitor holes, or a distance between three capacitor holes, or a distance between four capacitor holes, and the like.

12. A detection method, comprising:
obtaining a semiconductor structure, the semiconductor structure comprising a substrate and a capacitor support structure on the substrate, the capacitor support structure having a plurality of capacitor holes therein, the capacitor holes penetrating the capacitor support structure in a thickness direction of the capacitor support structure;
obtaining a set height and removing the capacitor support structure with the set height;
obtaining a test pattern, the test pattern being a pattern exposed at a top of the remaining capacitor support structure; and
determining a measurement interval in the test pattern, wherein the measurement interval comprising the capacitor holes in M rows and N columns, M and N being natural numbers greater than or equal to 2;
obtaining a plurality of spacings in a predetermined direction, wherein each spacing is a distance between the capacitor holes at predetermined positions in the measurement interval;
obtaining an offset range according to maximum and minimum ones of the plurality of spacings in a single row/column in the predetermined direction, the offset range indicating a distance between the maximum and minimum ones of the plurality of spacings; and
obtaining an offset distance, wherein the offset distance is an average of the plurality of offset ranges;
obtaining a yield of a products corresponding to the semiconductor structure; and
obtaining a first test relationship between the partial height which is a height of the capacitor support structure removed from the semiconductor structure and the offset distance under the yield;
according to the first test relat

Assignees

• Changxin Memory Tech Inc

Inventors

• Liu Xinran
• Wang Chunyang
• Zhu Changli

Classifications

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H01L22/20 Primary

  Electricity · mapped topic