Molded product for semiconductor strip and method of manufacturing semiconductor package

Patent metadata

Field	Value
Publication number	US-12308253-B2
Application number	US-202217862662-A
Country	US
Kind code	B2
Filing date	Jul 12, 2022
Priority date	Oct 25, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, comprising:
providing a substrate, the substrate having a first cutting region and a second cutting region respectively provided along a first side portion and a second side portion opposite each other and a mounting region between the first cutting region and the second cutting region, the substrate including adhesion reducing pads in the second cutting region;
disposing at least one semiconductor chip on the mounting region of the substrate;
forming a molding member on the substrate, the molding member including a sealing portion on the mounting region of the substrate and covering the at least one semiconductor chip, a dummy curl portion outside the second side portion of the substrate, and a plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion, the plurality of dummy runner portions being on the adhesion reducing pads to reduce an adhesive force between the substrate and the plurality of dummy runner portions; and
removing the dummy curl portion and at least portions of the dummy runner portions from the molding member.

2. The method of claim 1 , wherein each of the adhesion reducing pads includes at least two metal layers stacked on each other.

3. The method of claim 2 , wherein each of the metal layers of the adhesion reducing pads includes nickel (Ni) and gold (Au).

4. The method of claim 1 , wherein a thickness of at least one of the adhesion reducing pads is within a range of 2 μm to 10 μm.

5. The method of claim 1 , wherein the adhesion reducing pads include an organic coating layer.

6. The method of claim 5 , wherein the organic coating layer includes an organic solder mask (OSP).

7. The method of claim 5 , wherein a thickness of the organic coating layer is within a range of 0.1 μm to 0.3 μm.

8. The method of claim 1 , wherein a width of at least one of the adhesion reducing pads is within a range of 1 mm to 3 mm.

9. The method of claim 1 , wherein the molding member further includes a curl portion outside the first side portion of the substrate and a plurality of gate runner portions provided on the first cutting region to connect the sealing portion and the curl portion.

10. The method of claim 1 , further comprising:
removing the first cutting region and the second cutting region of the substrate.

11. A method of manufacturing a semiconductor package, comprising:
providing a substrate, the substrate having a first side portion and a second side portion opposite each other and a plurality of adhesion reducing pads spaced apart from each other along the second side portion;
disposing at least one semiconductor chip on the substrate;
disposing the substrate in a mold defining a cavity, a plurality of dummy runners, and dummy curl in fluid communication with each other,
the cavity configured to receive a sealing material for sealing the at least one semiconductor chip, the plurality of dummy runners configured to serve as pathways through which the sealing material is discharged from the cavity, and the dummy curl configured to be used for collecting the sealing material discharged through the dummy runners;

forming a molding member of the substrate by injecting the sealing material into the cavity of the mold and using the dummy curl for collecting the sealing material discharged from the cavity through the plurality of dummy runners,
the molding member including a sealing portion that covers the at least one semiconductor chip, a dummy curl portion outside the second side portion of the substrate, and a plurality of dummy runner portions connecting the sealing portion and the dummy curl portion,
the plurality of dummy runner portions respectively contacting portions of the adhesion reducing pads; and

removing the dummy curl portion and at least portions of the plurality of dummy runner portions from the molding member.

12. The method of claim 11 , wherein
the mold further includes a curl and a plurality of gate runners in fluid communication with each other and the cavity,
the curl is configured to receive the sealing material via injection, and
the plurality of gate runners are configured to serve as pathways through which the sealing material is introduced from the curl to the cavity.

13. The method of claim 12 , wherein
the molding member further includes a curl portion and a plurality of gate runner portions,
the curl portion is outside the first side portion of the substrate, and
the plurality of gate runner portions connect the sealing portion and the curl portion.

14. The method of claim 13 , further comprising:
removing the curl portion and at least portions of the plurality of gate runner portions from the molding member.

15. The method of claim 11 , wherein each of the adhesion reducing pads includes at least two metal layers stacked on each other.

16. The method of claim 11 , wherein the adhesion reducing pads include an organic coating layer.

17. The method of claim 16 , wherein the organic coating layer include an organic solder mask (OSP).

18. The method of claim 11 , wherein a width of at least one of the adhesion reducing pads is within a range of 1 mm to 3 mm.

19. The method of claim 11 , further comprising:
after the disposing the at least one semiconductor chip on the substrate, disposing an interposer substrate on the at least one semiconductor chip.

20. The method of claim 19 , further comprising:
disposing at least one second semiconductor chip on the interposer substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seunghwan
• Koh Kyonghwan
• Kim Jungjoo
• Kim Jongwan
• Park Junwoo
• Baek Hyunggil
• Lee Yongkwan
• Jang Dongju
• Jeon Taejun

Classifications

• H10W72/50

  Bond wires · CPC title

• H10P72/0441

  Apparatus for sealing, encapsulating, glassing, decapsulating or the like · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title