Semiconductor package and method

Patent metadata

Field	Value
Publication number	US-11049805-B2
Application number	US-201916266446-A
Country	US
Kind code	B2
Filing date	Feb 4, 2019
Priority date	Jun 29, 2018
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

First claim

What is claimed is:

1. A method comprising:
forming a first dielectric layer over a first metallization pattern;
forming a through via extending through the first dielectric layer, the through via electrically connected to the first metallization pattern;
treating a first surface of the first dielectric layer to form dangling hydroxyl groups on the first surface of the first dielectric layer, wherein treating the first surface of the first dielectric layer comprises:
performing a first surface treatment process to simultaneously etch and hydroxylate the first surface of the first dielectric layer; and
performing a second surface treatment process to remove residual metal exposed by etching the first surface of the first dielectric layer;
adhering a die to the first surface of the first dielectric layer;
after treating the first surface of the first dielectric layer and adhering the die to the first surface of the first dielectric layer, bonding an encapsulant to the first surface of the first dielectric layer with first covalent bonds using the dangling hydroxyl groups, the encapsulant laterally encapsulating the die and the through via;
forming a second dielectric layer over the encapsulant; and
forming a second metallization pattern extending through the second dielectric layer, the second metallization pattern electrically connected to the die and the through via.

2. The method of claim 1 further comprising:
forming first conductive connectors electrically connected to the first metallization pattern, a subset of the first conductive connectors overlapping an edge or a corner of the die; and
connecting a device package to the first metallization pattern with the first conductive connectors.

3. The method of claim 2 further comprising:
forming second conductive connectors electrically connected to the second metallization pattern, a subset of the second conductive connectors overlapping the edge or the corner of the die; and
connecting a package substrate to the second metallization pattern with the second conductive connectors.

4. The method of claim 1 , wherein bonding the encapsulant to the first surface of the first dielectric layer comprises:
dispensing the encapsulant on the first surface of the first dielectric layer, the encapsulant comprising a molding compound and a nucleophile; and
curing the encapsulant to form the first covalent bonds between the dangling hydroxyl groups and the nucleophile.

5. The method of claim 1 , wherein adhering the die to the first surface of the first dielectric layer comprises:
dispensing an adhesive on the die, the adhesive comprising an epoxy and a nucleophile; and
curing the adhesive to react the dangling hydroxyl groups and the nucleophile and form second covalent bonds.

6. The method of claim 1 , wherein the first surface treatment process is a plasma treatment process and the second surface treatment process is a wet etch process, wherein precursors of the plasma treatment process include O 2 and H 2 .

7. A method comprising:
plating a through via through a first dielectric layer with a seed layer;
etching exposed portions of the seed layer, residual metal of the seed layer remaining after etching the seed layer;
treating a first surface of the first dielectric layer to hydroxylate the first surface and remove the residual metal of the seed layer from the first surface, wherein treating the first surface of the first dielectric layer comprises:
performing a first surface treatment process to simultaneously etch and hydroxylate the first surface of the first dielectric layer; and
performing a second surface treatment process to remove the residual metal of the seed layer from the hydroxylated first surface;

adhering a die to the hydroxylated first surface; and
bonding an encapsulant to the hydroxylated first surface with first covalent bonds, the encapsulant laterally encapsulating the die and the through via; and
forming a second dielectric layer over the encapsulant and the die.

8. The method of claim 7 , wherein adhering the die to the hydroxylated first surface comprises:
bonding an adhesive to the hydroxylated first surface with second covalent bonds, the adhesive adhering the die to the hydroxylated first surface.

9. The method of claim 7 , wherein bonding the encapsulant to the hydroxylated first surface comprises:
dispensing the encapsulant on the hydroxylated first surface, the encapsulant comprising a molding compound and a nucleophile; and
curing the encapsulant to form the first covalent bonds between the hydroxylated first surface and the nucleophile.

10. The method of claim 7 , wherein the first surface treatment process decreases a thickness of the first dielectric layer, and the second surface treatment process does not decrease the thickness of the first dielectric layer.

11. The method of claim 7 further comprising:
forming the first dielectric layer over a metallization pattern;
forming a conductive connector electrically connected to the metallization pattern, the conductive connector overlapping a corner of the die; and
connecting a device package to the metallization pattern with the conductive connector.

12. The method of claim 7 further comprising:
forming the first dielectric layer over a metallization pattern;
forming a conductive connector electrically connected to the metallization pattern, the conductive connector overlapping an edge of the die; and
connecting a device package to the metallization pattern with the conductive connector.

13. The method of claim 9 , wherein the nucleophile is ethylene glycol, 2-ethoxyethanol, or ethanolamine hydrochloride.

14. A method comprising:
depositing a seed layer in an opening in a first dielectric layer and on a first surface of the first dielectric layer;
plating a conductive material from the seed layer;
etching exposed portions of the seed layer to form a through via comprising the conductive material and portions of the seed layer underlying the conductive material, wherein residual portions of the seed layer remain in the first surface of the first dielectric layer;
treating the first surface of the first dielectric layer to remove the residual portions of the seed layer and form dangling hydroxyl groups on the first surface of the first dielectric layer, wherein treating the first surface of the first dielectric layer comprises:
performing a plasma treatment process with O 2 and H 2 , wherein the plasma treatment process decreases a thickness of the first dielectric layer; and
performing a wet etch with hydrofluoric acid, wherein the wet etch does not decreases the thickness of the first dielectric layer;

adhering an integrated circuit die to the first surface of the first dielectric layer with an adhesive, the adhesive comprising a nucleophile;
dispensing an encapsulant on the first surface of the first dielectric layer, the encapsulant laterally surrounding the integrated circuit die and the through via, the encapsulant comprising the nucleophile; and
reacting the nucleophile with the dangling hydroxyl groups to form covalent bonds between the first dielectric layer and each of the adhesive and the encapsulant.

15. The method of claim 14 , wherein reacting the nucleophile with the dangling hydroxyl groups comprises curing the encapsulant.

16. The method of claim 14 further comprising:
forming a redistribution structure on the encapsulant, the integrated circuit die, and the through via;
connecting a conductive connector to the redistribution structure, the conductive connector laterally disposed ove

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Kuo Lung
• Chun Shu-Rong
• Lo Teng-Yuan
• Kuo Hung-Yi
• Chang Chih-Horng
• Kuo Tin-Hao
• Tsai Hao-Yi

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title