Pixel circuit, display panel, driving method and display device

US12307967B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12307967-B2
Application numberUS-202218262699-A
CountryUS
Kind codeB2
Filing dateMay 31, 2022
Priority dateMay 31, 2022
Publication dateMay 20, 2025
Grant dateMay 20, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit includes a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a writing-in control circuit; a first terminal of the first energy storage circuit is electrically connected to a control terminal of the driving circuit and a first terminal of the writing-in control circuit respectively, and a second terminal of the first energy storage circuit is electrically connected to a first terminal of driving circuit, a first terminal of the second energy storage circuit is electrically connected to a second terminal of the writing-in control circuit, and a second terminal of the second energy storage circuit is electrically connected to the writing-in terminal.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit, comprising a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a writing-in control circuit; wherein a first terminal of the first energy storage circuit is electrically connected to a control terminal of the driving circuit and a first terminal of the writing-in control circuit respectively, and a second terminal of the first energy storage circuit is electrically connected to a first terminal of driving circuit, a first terminal of the second energy storage circuit is electrically connected to a second terminal of the writing-in control circuit, and a second terminal of the second energy storage circuit is electrically connected to a writing-in terminal; the first energy storage circuit and the second energy storage circuit are used to store electrical energy; a control terminal of the writing-in control circuit is electrically connected to a first writing-in control terminal, and the writing-in control circuit is configured to control to connect or disconnect the first terminal of the first energy storage circuit and the first terminal of the second energy storage circuit under the control of a first writing-in control signal provided by the first writing-in control terminal; a second terminal of the driving circuit is electrically connected to the light emitting element, and the driving circuit is configured to generate a driving current for driving the light emitting element under the control of a potential of the control terminal of the driving circuit; the pixel circuit further comprises a first control circuit; wherein the first control circuit is electrically connected to a first control terminal, the first terminal of the second energy storage circuit, and the second terminal of the second energy storage circuit, is configured to control to connect or disconnect the first terminal of the second energy storage circuit and the second terminal of the second energy storage circuit under the control of a first control signal provided by the first control terminal. 2. The pixel circuit according to claim 1 , further comprising a second control circuit; the second control circuit is electrically connected to a second control terminal, a power supply voltage terminal and the first terminal of the driving circuit, and is configured to control to connect or disconnect the power supply voltage terminal and the first terminal of the driving circuit under the control of a second control signal provided by the second control terminal. 3. The pixel circuit according to claim 2 , wherein the second terminal of the driving circuit is electrically connected to a first electrode of the light emitting element, and a second electrode of the light emitting element is electrically connected to a first voltage terminal; the power supply voltage terminal is used to provide a power supply voltage, and the first voltage terminal is used to provide a first voltage signal; an absolute value of a voltage value of the power supply voltage is smaller than an absolute value of a voltage value of the first voltage signal. 4. The pixel circuit according to claim 1 , further comprising a third control circuit; wherein the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected to a first voltage terminal; the third control circuit is electrically connected to a third control terminal, a third voltage terminal and the first electrode of the light emitting element, and is configured to control to write a third voltage signal provided by the third voltage terminal into the first electrode of the light emitting element under the control of a third control signal provided by the third control terminal. 5. The pixel circuit according to claim 1 , further comprising a reference voltage writing-in circuit; wherein the reference voltage writing-in circuit is electrically connected to a second writing-in control terminal, a reference voltage terminal and a writing-in node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the writing-in node under the control of a second writing-in control signal provided by the second writing-in control terminal; the writing-in node is electrically connected to the control terminal of the driving circuit, or the writing-in node is electrically connected to the first terminal of the second energy storage circuit. 6. The pixel circuit according to claim 1 , further comprising a resistor circuit; wherein a first terminal of the resistor circuit is electrically connected to the second terminal of the driving circuit, and a second terminal of the resistor circuit is electrically connected to the first electrode of the light emitting element; the second electrode of the light emitting element is electrically connected to a first voltage terminal. 7. The pixel circuit according to claim 1 , wherein the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; a first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit and the first terminal of the writing-in control circuit, and a second terminal of the first capacitor is connected to the first terminal of the driving circuit; a first terminal of the second capacitor is electrically connected to the second terminal of the writing-in control circuit, and a second terminal of the second capacitor is electrically connected to the writing-in terminal; a capacitance value of the second capacitor is smaller than a capacitance value of the first capacitor. 8. The pixel circuit according to claim 1 , wherein the writing-in control circuit comprises a first transistor; a control electrode of the first transistor is electrically connected to the first writing-in control terminal, a first electrode of the first transistor is electrically connected to the control terminal of the driving circuit, and a second electrode of the first transistor is electrically connected to the first terminal of the second energy storage circuit; a back gate electrode of the first transistor is electrically connected to the second voltage terminal. 9. The pixel circuit according to claim 1 , wherein the first control circuit comprises a second transistor; a control electrode of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the first terminal of the second energy storage circuit, and a second electrode of the second transistor is electrically connected to the second terminal of the second energy storage circuit; a back gate electrode of the second transistor is electrically connected to the second voltage terminal. 10. The pixel circuit according to claim 5 , wherein the reference voltage writing-in circuit comprises a third transistor; a control electrode of the third transistor is electrically connected to the second writing-in control terminal, a first electrode of the third transistor is electrically connected to the reference voltage terminal, and a second electrode of the third transistor is electrically connected to the writing-in node; a back gate electrode of the third transistor is electrically connected to the second voltage terminal. 11. The pixel circuit according to claim 2 , wherein the second control circuit comprises a fourth transistor; the driving circuit comprises a driving transistor; a control electrode of the fourth transistor is ele

Assignees

Inventors

Classifications

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • being a dynamic memory with more than one capacitor · CPC title

  • Layout of electrodes and connections · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

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What does patent US12307967B2 cover?
A pixel circuit includes a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a writing-in control circuit; a first terminal of the first energy storage circuit is electrically connected to a control terminal of the driving circuit and a first terminal of the writing-in control circuit respectively, and a second terminal of the first …
Who is the assignee on this patent?
Yunnan Invensight Optoelectronics Technology Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 20 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).