Multiprocessor system with improved secondary interconnection network

Patent metadata

Field	Value
Publication number	US-12306773-B2
Application number	US-202318243943-A
Country	US
Kind code	B2
Filing date	Sep 8, 2023
Priority date	Dec 13, 2012
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

First claim

What is claimed is:

1. A method, comprising:
establishing a communication path on a primary interconnection network formed by a plurality of routers included in a multi-processor system that includes a plurality of processors coupled to the plurality of routers in an interspersed fashion, wherein the communication path identifies a subset of the plurality of routers;
receiving, by a bus controller, a response via a secondary interconnection network, wherein the response is responsive to a message from a first processor of the plurality of processors;
sending, by the bus controller, the response to a processor interface unit coupled to the bus controller;
by the processor interface unit:
in response to being sent the response, checking the response for an initialization command;
in response to a determination that the response includes the initialization command, comparing an address associated with the response to a hard-wired address associated with the processor interface unit; and
relaying the response to a first router of the plurality of routers; and

sending, by the first router, the response to the first processor via the primary interconnection network.

2. The method of claim 1 ,
wherein the processor interface unit comprises one or more buffers that are each configured to store responses received from the secondary interconnection network via the bus controller.

3. The method of claim 1 ,
wherein sending the response to the first processor comprises sending the response through one or more routers along the communication path before arriving at the first processor.

4. The method of claim 1 ,
wherein the secondary interconnection network comprises a plurality of processor interface units coupled together in a daisy chain fashion.

5. The method of claim 1 , wherein the bus controller is further configured to buffer the response.

6. The method of claim 1 , wherein the response includes a plurality of bits, and wherein a subset of the plurality of bits is associated with a command included in the response.

7. An apparatus, comprising:
a plurality of routers forming a primary interconnection network;
a plurality of interface units coupled together in a daisy chain fashion to form a secondary interconnection network;
a plurality of processors coupled to the plurality of routers in an interspersed fashion; and
a bus controller coupled to a first interface unit of the plurality of interface units and a first router of the plurality of routers each associated with a first processor of the plurality of processors, wherein the apparatus is configured to:
establish a communication path on the primary interconnection network, wherein the communication path identifies a subset of the plurality of routers;
receive, by the bus controller, a response via the secondary interconnection network, wherein the response is responsive to a message from the first processor;
send, by the bus controller, the response to the first interface unit;
in response to being sent the response and by the first interface unit, check the response for an initialization command;
in response to a determination that the response includes the initialization command and by the first interface unit, compare an address associated with the response to a hard-wired address associated with the first interface unit;

relay, by the first interface unit, the response to the first router; and
send, by the first router, the response to the first processor via the primary interconnection network.

8. The apparatus of claim 7 ,
wherein the first interface unit comprises one or more buffers that are each configured to store responses received from the secondary interconnection network via the bus controller.

9. The apparatus of claim 7 ,
wherein, in sending the response to the first processor, the bus controller is configured to send the response through one or more routers of the plurality of routers along the communication path before arriving at the first processor.

10. The apparatus of claim 7 , wherein the bus controller is further configured to buffer the response.

11. The apparatus of claim 7 , wherein the response includes a plurality of bits, and wherein a subset of the plurality of bits is associated with a command included in the response.

12. A multiprocessor system, comprising:
a plurality of processors, each comprising a plurality of processor ports;
a plurality of data memory routers, each comprising a plurality of communication ports, a first memory, and a routing engine;
wherein the plurality of processors and the plurality of data memory routers are coupled together in an interspersed fashion, wherein the plurality of data memory routers form a primary interconnection network;
a plurality of interface units, wherein each interface unit of the plurality of interface units is coupled to a respective processor and a respective data memory router, wherein the plurality of interface units are coupled together to form a secondary interconnection network;
a bus controller coupled to a first interface unit of the plurality of interface units, wherein the bus controller is configured to:
receive a response from the secondary interconnection network, wherein the response is responsive to a message from a first processor of the plurality of processors; and
send the response to the first interface unit;

wherein the first interface unit is configured to:
in response to being sent the response, check the response for an initialization command;
in response to a determination that the response includes the initialization command, compare an address associated with the response to a hard-wired address associated with the first interface unit; and
relay the response to a first data memory router of the plurality of routers; and

wherein the first data memory router is configured to send the response to the first processor via the primary interconnection network.

13. The multiprocessor system of claim 12 ,
wherein the first interface unit comprises one or more buffers that are each configured to store responses received from the secondary interconnection network via the bus controller.

14. The multiprocessor system of claim 12 ,
wherein, in sending the response to the first processor, the bus controller is configured to send the response through one or more routers of the plurality of routers along the communication path before arriving at the first processor.

15. The multiprocessor system of claim 12 , wherein the bus controller is further configured to buffer the response.

16. The multiprocessor system of claim 12 , wherein the response includes a plurality of bits, and wherein a subset of the plurality of bits is associated with a command included in the response.

17. The multiprocessor system of claim 12 , wherein the multiprocessor system further comprises a boot controller circuit.

18. The apparatus of claim 7 ,
wherein the secondary interconnection network comprises a plurality of processor interface units coupled together in a daisy chain fashion.

19. The apparatus of claim 7 ,
wherein the apparatus further comprises a boot controller circuit.

20. The multiprocessor system of claim 12 ,
wherein the secondary interconnection network comprises a plurality of processor interface units coupled together in a daisy chain fashion.

Assignees

• Coherent Logix Inc
• Hyperx Logic Inc

Inventors

• Dobbs Carl S
• Trocino Michael R

Classifications

• G06F15/7817

  Specially adapted for signal processing, e.g. Harvard architectures · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F13/4068

  Electrical coupling · CPC title