Multiprocessor system with improved secondary interconnection network

Patent metadata

Field	Value
Publication number	US-9612984-B2
Application number	US-201615043905-A
Country	US
Kind code	B2
Filing date	Feb 15, 2016
Priority date	Dec 13, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

First claim

What is claimed is:

1. A multiprocessor system, comprising:
a plurality of processors, each comprising a plurality of processor ports;
a plurality of memories;
a plurality of routers, wherein the plurality of routers form a primary interconnection network;
wherein the plurality of processors, the plurality of memories and the plurality of routers are coupled together in an interspersed fashion;
a plurality of interface units, wherein each interface unit is coupled to a respective processor and a respective router;
wherein the plurality of interface units are coupled together to form a secondary interconnection network; and
a bus controller coupled to at least one specified interface unit, wherein the bus controller is configured to:
send data to and receive data from the at least one specified interface unit;
arbitrate requests for access to the at least one specified interface unit; and
perform a comparison between messages received from each of two or more processors and perform a particular one of a plurality of actions based upon results of the comparison.

2. The multiprocessor system of claim 1 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send one of the messages to the secondary interconnect network in response to a determination that the messages received from each of the two or more processors match.

3. The multiprocessor system of claim 1 , further comprising an error handler unit.

4. The multiprocessor system of claim 3 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send a command to the error handler unit in response to a determination that the messages received from each of the two or more processors do not match.

5. The multiprocessor system of claim 4 , wherein the error handler unit is configured to report a tamper event in response to receiving the command from the bus controller.

6. The multiprocessor system of claim 4 , further comprising a plurality of Input/Output (I/O) circuits, wherein the error handler unit is configured to disable the I/O circuits in response to receiving the command from the bus controller.

7. The multiprocessor system of claim 4 , further comprising a plurality of fuses, wherein the error handler unit is configured to blow at least one fuse of the plurality of fuses in response to receiving the command from the bus controller.

8. A method for communicating in a multiprocessor system, wherein the multiprocessor system comprises a plurality of processors and a plurality of data memory routers coupled together in an interspersed fashion, the method comprising:
establishing a communication path on a primary interconnection network from a first processor to a specified router associated with a specified processor, wherein the specified router is connected to a processor interface block;
sending, by the first processor, a secondary interconnection network message through the primary interconnection network to the specified router;
providing, by the specified router, the secondary interconnection network message to the processor interface block;
providing, by the processor interface block, the secondary interconnection network message to a bus controller;
receiving, by the bus controller, messages from two or more the plurality of processors; and
performing, by the bus controller, a comparison of the messages from the two or more of the plurality of processors; and
performing a particular one of a plurality of actions based upon results of the comparison.

9. The method of claim 8 , wherein performing the particular one of the plurality of actions includes sending one of the messages to the secondary interconnect network in response to a determination that the messages received from each of the two or more processors match.

10. The method of claim 8 , wherein performing the particular one of the plurality of actions includes sending a command to an error handler unit included in the multiprocessor system in response to determining that the messages received from each of the two or more processors do not match.

11. The method of claim 10 , further comprising reporting, by the error handler unit, a tamper event in response to the error handler unit receiving the command from the bus controller.

12. The method of claim 10 , further comprising disabling, by the error handler unit, at least one Input/Output (I/O) circuit included in the multiprocessor system in response to the error handler unit receiving the command from the bus controller.

13. The method of claim 10 , further comprising blowing, by the error handler unit, at least one fuse of a plurality of fuses included in the multiprocessor system in response to the error handler unit receiving the command from the bus controller.

14. A multiprocessor system, comprising:
a plurality of processors, each comprising a plurality of processor ports;
a plurality of data memory routers, each comprising a plurality of communication ports, a first memory, and a routing engine;
wherein the plurality of processors and the plurality of data memory routers are coupled together in a interspersed fashion, wherein the plurality of data memory routers form a primary interconnection network;
a plurality of interface units, wherein each interface unit is coupled to a respective processor and a respective data memory router;
wherein the plurality of interface units are coupled together to form a secondary interconnection network; and
a bus controller coupled to at least a first interface unit and a second interface unit, wherein the bus controller is configured to:
send data to the first bus interface unit, and receive data from the second bus interface unit;
arbitrate requests for access to at least the first and second interface units;
perform a comparison between messages received from each of two or more processors of the plurality of processors; and
perform a particular one of a plurality of actions based upon results of the comparison.

15. The multiprocessor system of claim 14 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send one of the messages to the secondary interconnect network in response to a determination that the messages received from each of the two or more processors match.

16. The multiprocessor system of claim 14 , further comprising an error handler unit.

17. The multiprocessor system of claim 16 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send a command to the error handler unit in response to a determination that the messages received from each of the two or more processors do not match.

18. The multiprocessor system of claim 17 , wherein the error handler unit is configured to report a tamper event in response to receiving the command from the bus controller.

19. The multiprocessor system of claim 17 , further comprising a plurality of Input/Output (I/O) circuits, wherein the error handler unit is configured to disable the I/O circuits in response to receiving the command from the bus controller.

20. The multiprocessor system of claim 17 , further comprising a plurality of fuses, wherein the error handler unit is configured to blow at least one fuse of the plurality of fuses in response to receiving the command from the bus controller.

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R

Classifications

• G06F15/17381

  Two dimensional, e.g. mesh, torus · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F15/7882

  for self reconfiguration · CPC title

• G06F15/7817

  Specially adapted for signal processing, e.g. Harvard architectures · CPC title