Array substrate and display panel

Patent metadata

Field	Value
Publication number	US-12306509-B2
Application number	US-202318574261-A
Country	US
Kind code	B2
Filing date	Jan 10, 2023
Priority date	Jan 14, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

An array substrate and a display panel. The array substrate includes: a base substrate; a gate line and a data line on the base substrate, the gate line intersect the data line to define a pixel region; a metal oxide thin film transistor is arranged in the pixel region, the metal oxide thin film transistor includes a metal oxide semiconductor layer; the metal oxide semiconductor layer includes a first part and a second part; the first part and the data line are connected through a first via hole; the first part is in a stripe shape; a first included angle is between extension directions of the first part and the data line; an orthographic projection of the second part overlap with an orthographic projection of the gate line on the base substrate and do not overlap with an orthographic projection of the data line on the base substrate.

First claim

The invention claimed is:

1. An array substrate comprising:
a base substrate;
a gate line and a data line that are arranged on the base substrate, wherein the gate line intersects the data line to define a pixel region;
a metal oxide thin film transistor is arranged in the pixel region, and the metal oxide thin film transistor comprises a metal oxide semiconductor layer;
the metal oxide semiconductor layer comprises a first part and a second part which are connected with each other, the first part is connected to the data line through a first via hole, the first part is in a stripe shape, and a first included angle is between an extension direction of the first part and an extension direction of the data line, and the first included angle is greater than 0 degree and less than or equal to 90 degrees;
an orthographic projection of the second part on the base substrate overlaps with an orthographic projection of the gate line on the base substrate and does not overlap with an orthographic projection of the data line on the base substrate; and
a shape of the metal oxide semiconductor layer on a plane parallel to a main surface of the base substrate is a zigzag line, and a planar shape of a closed area formed by intersection of an orthographic projection of the metal oxide semiconductor layer, the orthographic projection of the data line and the orthographic projection of the gate line on the base substrate is a rectangle or a right trapezoid;
a width of the first part in the extension direction of the data line ranges from 10% to 50% of a width of the second part in an extension direction of the gate line, and an area of the first part ranges from 10% to 30% of an area of the second part.

2. The array substrate according to claim 1 , wherein
the metal oxide thin film transistor further comprises a first insulation layer, a light shielding layer, a first interlayer insulation layer, a gate insulation layer, a first gate electrode, a second interlayer insulation layer, a first drain electrode and a second insulation layer which are sequentially stacked on the base substrate, the metal oxide semiconductor layer is arranged between the first interlayer insulation layer and the gate insulation layer, the first gate electrode is connected with the gate line, and the second part is electrically connected with the first drain electrode.

3. The array substrate according to claim 2 , further comprising a driving transistor, wherein
the metal oxide thin film transistor is arranged in a display region, and the driving transistor is arranged in a peripheral region surrounding the display region;
the driving transistor comprises a polysilicon layer, the first insulation layer, a second gate electrode, the first interlayer insulation layer, the gate insulation layer and a source-drain electrode layer which are sequentially stacked on the base substrate, the source-drain electrode layer comprises a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are respectively electrically connected with the polysilicon layer.

4. The array substrate according to claim 1 , wherein the second part is in a stripe shape, an extension direction of the second part is the same as the extension direction of the data line, and the second part is between adjacent data lines in an extension direction of the gate line.

5. The array substrate according to claim 4 , wherein a first end of the second part away from the first part and a second end of the first part close to the second part are located at different sides of the gate line in the extension direction of the data line, and the second part is electrically connected with the first drain electrode at a position of the first end.

6. The array substrate according to claim 3 , wherein the second gate electrode is arranged in a same layer as the light shielding layer, and the source-drain electrode layer is arranged in a same layer as the first gate electrode.

7. The array substrate according to claim 1 , wherein a region where the metal oxide semiconductor layer and the first gate electrode are stacked is a channel region, and a remaining region is a conductive region, and a ratio of a length of the channel region to a length of the conductive region ranges from 1/5 to 1/4 along the extension direction of the data line.

8. The array substrate according to claim 1 , wherein the pixel region comprises pixels,

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Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Lizhong
• Yuan Guangcai
• Ning ce
• Xian Jianbo
• Lei Liping
• Long Chunping
• Di Yunping
• Tong Binbin
• Zhang Zhen

Classifications

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136222

  Colour filters incorporated in the active matrix substrate · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title