Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-10459302-B2
Application number	US-201715635014-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Feb 15, 2017
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

The present disclosure discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate; a plurality of scanning lines and a plurality of data lines located on one side of the substrate, the plurality of scanning lines are extended in a second direction, the plurality of data lines are extended in a first direction, the plurality of scanning lines intersect the plurality of data lines in an insulated manner; and a plurality of sub-pixels defined by the plurality of scanning lines and the plurality of data lines; where each of the plurality of sub-pixels includes a thin film transistor which comprises an active layer, a gate, a source and a drain, the active layer, the gate, the source and the drain are located on one side of the substrate. The active layer includes a channel region.

First claim

What is claimed is:

1. An array substrate comprising:
a substrate;
a plurality of scanning lines intersecting and insulated from a plurality of data lines on the substrate, wherein the plurality of data lines extends in a first direction and the plurality of scanning lines extends in a second direction; and
a plurality of sub-pixels defined by the plurality of scanning lines and the plurality of data lines, wherein the plurality of sub-pixels each comprises a thin film transistor having a gate, a source, a drain, and an active layer, wherein the active layer comprises at least one stripe-shaped portion extending along a first angle to the first direction, wherein the gate is disposed on one side of the active layer facing away from the substrate, wherein the active layer includes a channel region where the stripe-shaped portion of the active layer and the gate overlap in the direction perpendicular to the substrate;
wherein the channel region comprises two opposite edges parallel to each other in the second direction; and
wherein the first angle is equal to 10°.

2. The array substrate according to claim 1 , the two opposite edges in one of any two adjacent sub-pixels of the plurality of sub-pixels are parallel to the two opposite edges in the other of said two adjacent sub-pixels of the plurality of sub-pixels in the second direction.

3. The array substrate according to claim 1 , the sub-pixel further comprises a pixel electrode and a common electrode, wherein either the pixel electrode or the common electrode is a stripe-like electrode extending at a second angle from the first direction, wherein the second angle ranges from 0° to 20°.

4. The array substrate according to claim 3 , wherein the first angle equals to the second angle.

5. The array substrate according to claim 3 , wherein the second angle ranges from 5° to 10°.

6. The array substrate according to claim 3 , wherein the pixel electrode and the common electrode are stacked up, wherein the stripe-like electrode is always at the top of the other electrode.

7. The array substrate according to claim 6 , wherein the pixel electrode and the common electrode are stacked up alternately.

8. The array substrate according to claim 3 , wherein the second angle of said two adjacent sub-pixels are equal.

9. The array substrate according to claim 3 , wherein each of the plurality of data lines comprises a plurality of data line segments, wherein the plurality of data line segments each deviates from the first direction by the second angle of the adjacent sub-pixel.

10. The array substrate according to claim 3 , wherein each of the plurality of scanning lines comprises a plurality of scanning line segments, wherein each of the plurality of scanning line segments forms a third angle from the second direction, wherein the third angle equals the second angle of the adjacent sub-pixel.

11. The array substrate according to claim 1 , wherein each of the plurality of sub-pixels further comprises a light shield layer positioned between the substrate and the active layer, and the light shield layers of any two adjacent sub-pixels are insulated from each other, and the orthographic projection of the light shield layer on the substrate completely overlaps the orthographic projection of the channel region on the substrate.

12. The array substrate according to claim 11 , wherein the active layer comprises two stripe-like portions and a connector to form a U-shape, the two stripe-like portions and the gate overlap to form two channel regions.

13. The array substrate according to claim 12 , wherein each of the light shield layers has a light shield pattern, and the orthographic projection of the light shield pattern on the substrate completely overlaps the orthographic projection of the two channel regions on the substrate.

14. The array substrate according to claim 12 , wherein each of the light shield layers comprises two light shield patterns mutually insulated, the orthographic projection of each of the light shield patterns on the substrate completely overlaps the orthographic projection of one of the channel regions on the substrate.

15. A display panel comprising an array substrate, the array substrate comprising:
a substrate;
a plurality of scanning lines intersecting and insulated from a plurality of data lines on the substrate, wherein the plurality of data lines extends in a first direction and the plurality of scanning lines extends in a second direction; and
a plurality of sub-pixels defined by the plurality of scanning lines and the plurality of data lines, wherein the plurality of sub-pixels each comprises a thin film transistor having a gate, a source, a drain, and an active layer, wherein the active layer comprises at least one stripe-shaped portion extending along a first angle to the first direction, wherein the gate is disposed on one side of the active layer facing away from the substrate, wherein the active layer includes a channel region where the stripe-shaped portion of the active layer and the gate overlap in the direction perpendicular to the substrate;
wherein the channel region comprises two opposite edges parallel to each other in the second direction; and
wherein the first angle is equal to 10°.

16. A display device comprising a display panel, the display panel comprising an array substrate, the array substrate comprising:
a substrate;
a plurality of scanning lines intersecting and insulated from a plurality of data lines on the substrate, wherein the plurality of data lines extends in a first direction and the plurality of scanning lines extends in a second direction; and
a plurality of sub-pixels defined by the plurality of scanning lines and the plurality of data lines, wherein the plurality of sub-pixels each comprises a thin film transistor having a gate, a source, a drain, and an active layer, wherein the active layer comprises at least one stripe-shaped portion extending along a first angle to the first direction, wherein the gate is disposed on one side of the active layer facing away from the substrate, wherein the active layer includes a channel region where the stripe-shaped portion of the active layer and the gate overlap in the direction perpendicular to the substrate;
wherein the channel region comprises two opposite edges parallel to each other in the second direction; and
wherein the first angle is equal to 10°.

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Zhang Lei

Classifications

• G02F1/133707

  Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

• G02F2201/124

  interdigital · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title