Substrate, backlight module and display device

Patent metadata

Field	Value
Publication number	US-12306495-B2
Application number	US-202218692405-A
Country	US
Kind code	B2
Filing date	Aug 26, 2022
Priority date	Aug 26, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A substrate includes a circuit board and a first reflective layer. The first reflective layer is disposed on the substrate. The first reflective layer has a central region and a peripheral region surrounding the central region. The first reflective layer includes at least one first buffer structure group, and an orthogonal projection of the first buffer structure group on the circuit board falls into the peripheral region. Each first barrier structure group includes a plurality of first slits spaced apart from each other, and a plurality of first slits in any first buffer structure group are disposed around the central region.

First claim

What is claimed is:

1. A substrate, comprising:
a circuit board; and
a first reflective layer disposed on the circuit board; the first reflective layer having a central region and a peripheral region surrounding the central region; the first reflective layer including at least one first buffer structure group and at least one second buffer structure group, an orthogonal projection of the at least one first buffer structure group on the circuit board falling into the peripheral region, and an orthogonal projection of the at least one second buffer structure group on the circuit board falling into the peripheral region; wherein
each first buffer structure group includes a plurality of first slits spaced apart from each other, and a plurality of first slits in any first buffer structure group are disposed around the central region; and
each second buffer structure group includes at least one second slit extending in a direction perpendicular to a boundary of the central region.

2. The substrate according to claim 1 , wherein the at least one first buffer structure group includes a plurality of first buffer structure groups, any two adjacent first buffer structure groups have an interval therebetween, and centers of the plurality of first buffer structure groups coincide with a geometric center of the central region.

3. The substrate according to claim 2 , wherein in two adjacent first buffer structure groups, first slits in the two adjacent first buffer structure groups are disposed in a staggered manner in a direction perpendicular to a boundary of the central region and parallel to a plane where the circuit board is located.

4. The substrate according to claim 3 , wherein all first slits in the first buffer structure group are connected end to end in a clockwise or counterclockwise direction to be a first enclosed pattern; and
the first enclosed pattern has a first circumference, a first length accounts for at least ¼ of the first circumference, and the first length is a sum of lengths of the plurality of first slits in the first buffer structure group.

5. The substrate according to claim 1 , wherein
the at least one slit includes a plurality of second slits, and the plurality of second slits extend in a same direction and are spaced apart from each other.

6. The substrate according to claim 5 , wherein the at least one second buffer structure group includes a plurality of second buffer structure groups, the plurality of second buffer structure groups are disposed at intervals on a periphery of the central region of the first reflective layer, and second slits in two adjacent second buffer structure groups are disposed in a staggered manner; and/or
any second buffer structure group intersects with at least one first buffer structure group.

7. The substrate according to claim 1 , further comprising a plurality of electronic components, wherein the substrate has a plurality of functional regions, and each functional region is provided thereon with multiple electronic components connected in series and/or in parallel;
a first slit is located between two adjacent functional regions; and
a second slit is located between the two adjacent functional regions.

8. The substrate according to claim 1 , wherein an area of the peripheral region accounts for 15% to 25% of an area of a surface of the first reflective layer parallel to the circuit board.

9. The substrate according to claim 1 , further comprising:
a plurality of electronic components disposed on the circuit board; and
a plurality of encapsulation portions, an encapsulation portion wrapping at least one electronic component; wherein the first reflective layer further includes a plurality of hollow regions and at least one third buffer structure group; an electronic component is located in a hollow region, and the encapsulation portion covers at least one hollow region; each third buffer structure group includes a plurality of third slits spaced apart from each other, and multiple third slits in a third buffer structure group are disposed around the encapsulation portion.

10. The substrate according to claim 9 , wherein the at least one third buffer structure group includes a plurality of third buffer structure groups, at least two third buffer structure groups are disposed around the same encapsulation portion, and in the at least two third buffer structure groups, any two adjacent third buffer structure groups have an interval therebetween.

11. The substrate according to claim 10 , wherein centers of the at least two third buffer structure groups disposed around the same encapsulation portion coincide with a geometric center of the encapsulation portion; and/or
in two adjacent third buffer structure groups, third slits in the two adjacent third buffer structure groups are disposed in a staggered manner in a direction perpendicular to a boundary of the hollow region and parallel to a plane where the circuit board is located.

12. The substrate according to claim 9 , wherein all third slits in each third buffer structure group are connected end to end in a clockwise or counterclockwise direction to be a second enclosed pattern; an outer boundary of an orthogonal projection of the encapsulation portion on the circuit board constitutes a third enclosed pattern; and an outer boundary of an orthogonal projection of the hollow region on the circuit board constitutes a fourth enclosed pattern; wherein
at least two of the second enclosed pattern, the third enclosed pattern and the fourth enclosed pattern are similar figures to each other.

13. The substrate according to claim 12 , wherein the second enclosed pattern and the third enclosed pattern are each in a shape of a circle; and
a ratio of a diameter of a second enclosed pattern corresponding to a third buffer structure group closest to the encapsulation portion to a diameter of the encapsulation portion is greater than 1 and less than or equal to 1.2; and/or
at least two third buffer structure groups are disposed around the same encapsulation portion, and in the at least two third buffer structure groups, a ratio of a difference between diameters of two second enclosed patterns corresponding to any two adjacent third buffer structure groups to the diameter of the encapsulation portion is greater than 0 and less than or equal to 0.2.

14. The substrate according to claim 12 , wherein the second enclosed pattern is in a shape of a polygon, and the third enclosed pattern is in a shape of a circle;
a ratio of a length of a diagonal of a second enclosed pattern corresponding to a third buffer structure group closest to the encapsulation portion to a diameter of the encapsulation portion is greater than 1 and less than or equal to 1.2; and/or
at least two third buffer structure groups are disposed around the same encapsulation portion, and in the at least two third buffer structure groups, a ratio of a difference between lengths of diagonals of two second enclosed patterns corresponding to any two adjacent third buffer structure groups to the diameter of the encapsulation portion is greater than 0 and less than or equal to 0.2.

15. The substrate according to claim 9 , wherein all third slits in each third buffer structure group are connected end to end in a clockwise or counterclockwise direction to be a second enclosed pattern; and
the second enclosed pattern has a second circumference, a second length accounts for at least ¼ of the second circumference, and the second length is a sum of lengths of the multiple third slits in the third buffer structure group.

16. The substrate according to cla

Assignees

• Hefei Boe Ruisheng Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Chenyang
• Wang Kangli
• Zhang Bing

Classifications

• G02F1/133603

  with LEDs · CPC title

• G02F1/133612 Primary

  Electrical details · CPC title

• H10H20/856

  Reflecting means · CPC title

• G02F1/133605 Primary

  including specially adapted reflectors · CPC title