Memory device and method of manufacturing the memory device

Patent metadata

Field	Value
Publication number	US-12302547-B2
Application number	US-202217826812-A
Country	US
Kind code	B2
Filing date	May 27, 2022
Priority date	Dec 20, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

Provided herein may be a memory device and a method of manufacturing the memory device. The memory device may include a connection structure formed on a substrate, lower contacts formed on the connection structure, upper contacts formed on the lower contacts, a dummy pattern configured to enclose the lower contacts and spaced apart from the lower contacts, etching stop patterns formed in an upper region of the dummy pattern, and dummy contacts formed over the etching stop patterns.

First claim

What is claimed is:

1. A memory device, comprising:
a connection structure formed on a substrate;
lower contacts formed on the connection structure;
upper contacts formed on the lower contacts;
a dummy pattern configured to enclose the lower contacts and spaced apart from the lower contacts;
etching stop patterns formed in an upper region of the dummy pattern; and
dummy contacts formed over the etching stop patterns.

2. The memory device according to claim 1 , further comprising:
a transistor configured to transfer or block a voltage between the connection structure and the lower contacts.

3. The memory device according to claim 1 , wherein the lower contacts contact the connection structure by vertically passing through an insulating pattern enclosed by the dummy pattern.

4. The memory device according to claim 1 , wherein the upper contacts contact the lower contacts by vertically passing through a stacked structure formed over the lower contacts, the dummy pattern, and the etching stop patterns.

5. The memory device according to claim 1 , wherein the lower contacts and the upper contacts are used as main contacts that are electrically connected to a ground terminal formed in the substrate through the connection structure.

6. The memory device according to claim 1 , wherein the lower contacts, the upper contacts, and the dummy contacts are formed of an identical material.

7. The memory device according to claim 1 , wherein widths of the upper contacts are equal to widths of the dummy contacts.

8. The memory device according to claim 1 , wherein the dummy pattern comprises:
a first conductive layer;
a first insulating layer formed on the first conductive layer;
a second conductive layer formed on the first insulating layer;
a second insulating layer formed on the second conductive layer; and
a third conductive layer formed on the second insulating layer.

9. The memory device according to claim 1 , wherein the etching stop patterns are formed of a conductive material.

10. The memory device according to claim 1 , wherein the etching stop patterns are formed of at least one of tungsten (W), titanium (Ti), and titanium nitride (TiN).

11. A method of manufacturing a memory device, comprising:
providing a substrate in which a cell region and a peripheral region are defined;
forming conductive patterns on the substrate of the cell region and the peripheral region;
forming a lower contact between the conductive patterns in the peripheral region;
forming etching stop patterns in the conductive patterns in the cell region and the peripheral region;
forming a stacked structure on the etching stop patterns;
forming holes configured to respectively expose the lower contact and the etching stop pattern in the stacked structure in the peripheral region; and
forming a dummy contact contacting portions of the etching stop patterns and an upper contact contacting the lower contact by filling the holes formed in the peripheral region with a conductive material.

12. The method according to claim 11 , further comprising:
before forming the conductive patterns on the substrate,
forming a junction region in the substrate; and
forming a connection structure on the junction region.

13. The method according to claim 12 , wherein the lower contact is formed to contact the connection structure.

14. The method according to claim 11 , wherein:
patterns formed in the cell region, among the etching stop patterns, are formed along a direction in which a slit separating memory blocks extends, and
patterns formed in the peripheral region, among the etching stop patterns, are formed in a region in which the dummy contact is to be formed.

15. The method according to claim 11 , wherein the etching stop patterns are formed of at least one of tungsten (W), titanium (Ti), and titanium nitride (TiN).

16. The method according to claim 11 , wherein the etching stop patterns are formed of a mixture of at least two of tungsten (W), titanium (Ti), and titanium nitride (TiN).

17. The method according to claim 11 , wherein forming the holes is performed by an etching process for removing a portion of the stacked structure in a vertical direction.

18. The method according to claim 11 , further comprising:
between forming the stacked structure and forming the holes,
forming cell plugs passing through the stacked structure in the cell region;
forming a slit exposing the etching stop pattern by passing through the stacked structure between the cell plugs;
forming a recess by removing the etching stop pattern and a portion of the conductive pattern formed below the slit;
filling the recess with a conductive material;
removing sacrificial patterns included in the stacked structure in the cell region; and
forming gate lines in regions from which the sacrificial patterns are removed.

19. The method according to claim 18 , wherein forming the cell plugs comprises:
forming a vertical hole passing through the stacked structure formed in the cell region; and
forming a blocking layer, a charge trap layer, a tunnel isolation layer, a channel layer, and a core pillar from a side surface of the vertical hole.

20. The method according to claim 18 , wherein forming the slit is performed by an etching process for separating the stacked structure formed in the cell region in a first direction.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek

Classifications

• H10B12/312

  with a bit line higher than the capacitor · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title