Frequency-division multiplexing

Patent metadata

Field	Value
Publication number	US-12301276-B2
Application number	US-202117554922-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Feb 5, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A method is provided. In some examples, the method includes generating, by processing circuitry, a spread of chips representing an input bit. In addition, the method includes converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a pair of symbols. The method also includes mapping, by the processing circuitry, the pair of symbols to a single carrier signal and generating, by the processing circuitry, a radio-frequency (RF) signal based on the single carrier signal. The method further includes transmitting, by the processing circuitry via an antenna, the RF signal.

First claim

What is claimed is:

1. A method comprising:
generating, by processing circuitry, a spread of chips representing an input bit, wherein generating the spread of chips comprises generating two consecutive chips representing the input bit, wherein matching values for the two consecutive chips represents a first value of the input bit, and wherein non-matching values for the two consecutive chips represents a second value of the input bit different from the first value;
converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a pair of symbols;
mapping, by the processing circuitry, the pair of symbols to a single carrier signal;
generating, by the processing circuitry, a radio-frequency (RF) signal based on the single carrier signal; and
transmitting, by the processing circuitry via an antenna, the RF signal.

2. The method of claim 1 ,
wherein the pair of symbols is a first pair of symbols,
wherein the single carrier signal is a first carrier signal, and
wherein the plurality of symbols further comprises a second pair of symbols,
the method further comprising mapping the second pair of symbols to a second carrier signal different from the first carrier signal.

3. The method of claim 2 ,
wherein the first pair of symbols encodes a value of the input bit, and
wherein the second pair of symbols encodes the value of the input bit.

4. The method of claim 3 , wherein transmitting the RF signal comprises transmitting the RF signal at a first time using a first channel centered on a first frequency, the method further comprising:
generating a second RF signal based on the second carrier signal; and
transmitting the RF signal at a second time using a second channel centered on a second frequency that is different from the first frequency.

5. The method of claim 1 , wherein converting the spread of chips into the plurality of symbols comprises performing binary phase shift keying on the spread of chips.

6. The method of claim 1 , wherein the plurality of symbols comprises orthogonal frequency-division multiplexing (OFDM) symbols.

7. The method of claim 1 , further comprising adding a cyclic prefix and a guard interval between the pair of symbols.

8. A method comprising:
generating, by processing circuitry, a first spread of chips representing a first input bit;
converting, by the processing circuitry, the first spread of chips to a plurality of symbols comprising a pair of symbols;
mapping, by the processing circuitry, the pair of symbols to a single carrier signal;
generating, by the processing circuitry, a radio-frequency (RF) signal based on the single carrier signal;
transmitting, by the processing circuitry via an antenna, the RF signal; and
generating a second spread of chips representing a second input bit after generating the first spread of chips, wherein a logical value of the second input bit is identical to a logical value of the first input bit, and wherein logical values of the second spread of chips are opposite of logical values of the first spread of chips.

9. The method of claim 8 , further comprising generating a third spread of chips representing a third input bit after generating the second spread of chips,
wherein a logical value of the third input bit is identical to a logical value of the second input bit,
wherein logical values of the third spread of chips are opposite of logical values of the second spread of chips, and
wherein logical values of the third spread of chips are identical to logical values of the first spread of chips.

10. A method comprising:
generating, by processing circuitry, a spread of chips representing an input bit;
converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a first pair of symbols and a second pair of symbols;
mapping, by the processing circuitry, the first pair of symbols to a first carrier signal;
mapping the second pair of symbols to a second carrier signal different from the first carrier signal;
generating, by the processing circuitry, a first radio-frequency (RF) signal based on the first and second carrier signals;
transmitting, by the processing circuitry via an antenna, the first RF signal the first RF signal at a first time;
generating a second RF signal based on the second carrier signal including the second pair of symbols; and
transmitting the second RF signal at a second time after the first time.

11. A method comprising:
generating, by processing circuitry, a spread of chips representing an input bit;
converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a first pair of symbols and a second pair of symbols;
mapping, by the processing circuitry, the first pair of symbols to a first carrier signal;
mapping the second pair of symbols to a second carrier signal different from the first carrier signal;
generating, by the processing circuitry, a first radio-frequency (RF) signal based on the first and second carrier signals; and
transmitting, by the processing circuitry via an antenna, the first RF signal, wherein a first frequency band of the first carrier signal is orthogonal to a second frequency band of the second carrier signal.

12. A method comprising:
generating, by processing circuitry, a spread of chips representing an input bit;
converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a first pair of symbols representing the input bit and a second pair of symbols representing the input bit, wherein the second pair of symbols is different from the first pair of symbols;
selecting a first channel centered on a first frequency;
mapping the first pair of symbols to a first carrier signal in the first channel;
generating a first radio-frequency (RF) signal based on the first carrier signal;
transmitting the first RF signal at a first time;
selecting a second channel centered on a second frequency different from the first frequency;
mapping the second pair of symbols to a second carrier signal in the second channel;
generating a second RF signal based on the second carrier signal; and
transmitting the second RF signal at a second time after the first time.

13. A method comprising:
generating, by processing circuitry, a spread of chips representing an input bit, wherein generating the spread of chips comprises generating two consecutive chips representing the input bit, wherein matching values for the two consecutive chips represents a first value of the input bit, and wherein non-matching values for the two consecutive chips represents a second value of the input bit different from the first value;
converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a pair of symbols;
adding a cyclic prefix and a guard interval between the pair of symbols;
mapping, by the processing circuitry, the pair of symbols to a single carrier signal;
performing, by the processing circuitry, an inverse transform on the single carrier signal including the mapped pair of symbols to generate a radio-frequency (RF) signal; and
transmitting, by the processing circuitry via an antenna, the RF signal.

14. A computing system comprising:
processing circuitry; and
a non-transitory computer-readable medium coupled to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the processing circuitry to:
generate a spread of chips representing an input bit, wherein the instructions to generate the spread of chips comprise instructions to generate two consecutive chips representing th

Assignees

• Texas Instruments Inc

Inventors

• Motos Tomas
• Almholt Thomas

Classifications

• H04L27/103

  Chirp modulation (for spread spectrum techniques H04B1/69) · CPC title

• H04B2001/6912

  using chirp · CPC title

• H04L5/0007

  the frequencies being orthogonal, e.g. OFDM(A) or DMT · CPC title

• H04L27/32

  Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26 · CPC title

• H04L27/20

  Modulator circuits; Transmitter circuits · CPC title