DSSS inverted spreading for smart utility networks

Patent metadata

Field	Value
Publication number	US-9831909-B2
Application number	US-201615066549-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Jul 16, 2012
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A method of operating a transmitter (FIGS. 3 A and 5 A) is disclosed. The method includes receiving a sequence of data bits (DATA), wherein each data bit has a respective sequence number. A first data bit of the sequence is spread ( 508 ) with a first spreading code ( 504 ) determined by the sequence number ( 502 ) of the first data bit. A second data bit of the sequence is spread ( 508 ) with an inverse of the first spreading code ( 506 ) determined by the sequence number ( 502 ) of the second data bit. The first and second data bits are modulated ( 510 ) and transmitted ( 516 ) to a remote receiver.

First claim

What is claimed is:

1. A method, comprising:
receiving, by a buffer, a sequence of data bits, each data bit having a respective sequence number;
spreading, by an XOR circuit, a first data bit of the sequence into spread first data bits using a first spreading code determined by the sequence number of the first data bit;
providing, by a memory circuit, a second spreading code by inversing the first spreading code based on the sequence number of a second data bit; and
spreading, by the XOR circuit, the second data bit of the sequence into spread second data bits using the second spreading code.

2. The method of claim 1 , wherein:
the first data bit has an even sequence number; and
the second data bit has an odd sequence number.

3. The method of claim 1 , further comprising:
scrambling, by a second XOR circuit, the first and second data bits with a scrambling code.

4. The method of claim 1 , further comprising:
applying, by a modulator, an offset quadrature phase shift keyed (O-QPSK) modulation to the spread first and second data bits.

5. The method of claim 1 , wherein the first spreading code includes four chips.

6. A method, comprising:
receiving, by a buffer, a sequence of data bits, each data bit having a respective sequence number;
inverting, by an inverter, a first data bit of the sequence in response to the sequence number of the first data bit;
spreading, by an XOR circuit while coupled to the inverter, the inverted first data bit into spread first data bits using a spreading code; and
spreading, by the XOR circuit while coupled to the buffer, a second data bit into spread second data bits of the sequence using the spreading code.

7. The method of claim 6 , wherein:
the first data bit has an odd sequence number; and
the second data bit has an even sequence number.

8. The method of claim 6 , further comprising:
scrambling, by a second XOR circuit, the first and second data bits with a scrambling code.

9. The method of claim 6 , further comprising:
applying, by a modulator, an offset quadrature phase shift keyed (O-QPSK) modulation to the spread first and second data bits.

10. The method of claim 6 , wherein the spreading code includes at least four chips.

11. A method, comprising:
storing, by a memory circuit, a first despreading code and a second despreading code inversing the first despreading code;
receiving, by an XOR circuit, a first and second groups of spread data bits, each group of spread data bits having a respective sequence number;
despreading, by the XOR circuit, the first group of spread data bits sharing a first sequence number to generate a first data bit using the first despreading code determined by the first sequence number; and
despreading, by the XOR circuit, the second group of spread data bits to generate a second data bit using the second despreading code.

12. The method of claim 11 , wherein:
the first sequence number is an even number; and
the second sequence number is an odd number.

13. The method of claim 11 , further comprising:
descrambling, by a second XOR circuit, a first group of scrambled data bits and a second group of scrambled data bits to the first group of spread data bits and the second group of spread data bits respectively with a descrambling code.

14. The method of claim 11 , further comprising:
applying, by a demodulator, an offset quadrature phase shift keyed (O-QPSK) demodulation for generating the first and second groups of spread data bits.

15. The method of claim 11 , wherein the first despreading code includes at least four chips.

16. A method, comprising:
storing, by a memory circuit, a despreading code;
receiving, by an XOR circuit, a first and second groups of spread data bits, each group of spread data bits having a respective sequence number;
despreading, by the XOR circuit, the first group of spread data bits to generate a first data bit using a spreading code;
despreading, by the XOR circuit, the second group of spread data bits to generate a second data bit using the spreading code; and
inverting, by an inverter, the second data bit in response to the sequence number of the second group of spread data bits.

17. The method of claim 16 , wherein:
the first group of spread data bits share an even sequence number; and
the second group of spread data bits share an odd sequence number.

18. The method of claim 16 , further comprising:
descrambling, by a second XOR circuit, a first group of scrambled data bits and a second group of scrambled data bits to the first group of spread data bits and the second group of spread data bits respectively with a descrambling code.

19. The method of claim 16 , further comprising:
applying, by a demodulator, an offset quadrature phase shift keyed (Q-QPSK) demodulation for generating the first and second groups of spread data bits.

20. The method of claim 16 , wherein the despreading code includes at least four chips.

21. A transmitter, comprising:
means for receiving a sequence of data bits, each data bit having a respective sequence number;
means for storing a first spreading code and a second spreading code inversing the first spreading code;
means for spreading a first data bit of the sequence into spread first data bits using the first spreading code determined by the sequence number of the first data bit; and
means for spreading a second data bit of the sequence into spread second data bits using the second spreading code determined by the sequence number of the second data bit.

22. The transmitter of claim 21 , wherein:
the first data bit has an even sequence number; and
the second data bit has an odd sequence number.

23. The transmitter of claim 21 , further comprising:
means for scrambling the first and second spread data bits with a scrambling code.

24. The transmitter of claim 21 , further comprising:
means for applying an offset quadrature phase shift keyed (O-QPSK) modulation to the spread first and second data bits.

25. The transmitter of claim 21 , wherein the first spreading code includes four chips.

26. A transmitter, comprising:
means for receiving a sequence of data bits, each data bit having a respective sequence number;
means for inverting a first data bit of the sequence in response to the sequence number of the first data bit;
means for spreading the inverted first data bit into spread first data bits using a spreading code; and
means for spreading a second data bit into spread second data bits of the sequence using the spreading code.

27. The transmitter of claim 26 , wherein:
the first data bit has an odd sequence number; and
the second data bit has an even sequence number.

28. The transmitter of claim 26 , further comprising:
means for scrambling the first and second spread data bits with a scrambling code.

29. The transmitter of claim 26 , further comprising:
means for applying offset quadrature phase shift keyed (O-QPSK) modulation to the spread first and second data bits.

30. The transmitter of claim 26 , wherein the spreading code includes at least four chips.

31. A receiver, comprising:
means for storing a first despreading code and a second despreading code inversing the first despreading code; and
means for receiving a first and second groups of spread data bits, each group of sp

Assignees

• Texas Instruments Inc

Inventors

• Schmidl Timothy Mark
• Dabak Anand G

Classifications

• H04L5/0048

  Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091) · CPC title

• H04B1/707 Primary

  using direct sequence modulation · CPC title

• H04L27/22

  Demodulator circuits; Receiver circuits · CPC title

• H04B1/7085

  using a code tracking loop, e.g. a delay-locked loop · CPC title