Pixel driving circuit, pixel driving method and display panel

Patent metadata

Field	Value
Publication number	US-12300167-B2
Application number	US-202117914844-A
Country	US
Kind code	B2
Filing date	Sep 29, 2021
Priority date	Sep 29, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

The present disclosure provides a pixel driving circuit, a pixel driving method and a display panel, relating to a field of display technology. The pixel driving circuit includes a driving transistor; a storage capacitor connecting a first node and a second node; a data writing unit configured to output a data voltage to the second node in response to a first scan signal; a light emitting control unit configured to electrically communicate a third node and a fourth node in response to a light emitting control signal; a first reset unit configured to output a reference voltage to the second node in response to the light emitting control signal or a first reset signal; a second reset unit configured to output an initialization voltage to the first node in response to a second reset signal.

First claim

What is claimed is:

1. A pixel driving circuit comprising:
a driving transistor connected to a first node and a third node;
a storage capacitor connected to the first node and a second node;
a data writing circuit connected to the second node, configured to output a data voltage to the second node in response to a first scan signal;
a light emitting control circuit connected to the third node and a fourth node, configured to electrically communicate the third node with the fourth node in response to a light emitting control signal;
a first reset circuit connected to the second node, configured to output a reference voltage to the second node in response to the light emitting control signal or a first reset signal;
a second reset circuit connected to the first node, configured to output an initialization voltage to the first node in response to a second reset signal;
wherein the pixel driving circuit is arranged on a side of a base substrate;
the storage capacitor comprises a first electrode plate, a second electrode plate, a third electrode plate and a fourth electrode plate sequentially stacked on the side of the base substrate, and an insulating medium is sandwiched between any two adjacent electrode plates; the first electrode plate and the third electrode plate are both electrically connected to the first node; the second electrode plate and the fourth electrode plate are both electrically connected to the second node;
wherein the pixel driving circuit is applied to a display panel, and the display panel comprises the base substrate;
the display panel further comprises a first passivation layer and a first planarization layer sequentially stacked on a side of the third electrode plate away from the base substrate, and the fourth electrode plate is arranged on a side of the first planarization layer away from the base substrate;
the first planarization layer comprises at least a first portion and a second portion, and the first portion of the first planarization layer is sandwiched between the third electrode plate and the fourth electrode plate; the second portion of the first planarization layer does not overlap with the third electrode plate and the fourth electrode plate; and a thickness of the first portion is less than a thickness of the second portion.

2. The pixel driving circuit according to claim 1 , further comprising:
a third reset circuit connected to the fourth node, configured to output the initialization voltage to the fourth node in response to the first reset signal.

3. The pixel driving circuit according to claim 1 , further comprising a threshold compensation circuit connected to the first node and the third node, configured to electrically communicate the first node with the third node in response to a second scan signal, wherein the threshold compensation circuit comprises:
a second transistor comprising a first electrode connected to the third node, a second electrode connected to the first node and a gate configured to load the second scan signal;
the second reset circuit comprises:
a fourth transistor comprising a first electrode configured to load the initialization voltage, a second electrode connected to the first node, and a gate configured to load the second reset signal; and
materials of active layers of the second transistor and the fourth transistor are both metal oxide semiconductor materials.

4. The pixel driving circuit according to claim 3 , wherein the gate of the second transistor comprises a first gate and a second gate both configured to load the second scan signal, and the active layer of the second transistor comprises a channel region; the first gate, the channel region, and the second gate of the second transistor are sequentially stacked;
the gate of the fourth transistor comprises a first gate and a second gate both configured to load the second reset signal, and the active layer of the fourth transistor comprises a channel region; the first gate, the channel region, and the second gate of the fourth transistor are sequentially stacked.

5. The pixel driving circuit according to claim 4 , wherein the pixel driving circuit is arranged on a side of a base substrate;
the first gate of the second transistor is located on a side of the channel region of the second transistor close to the base substrate; an orthographic projection of the second gate of the second transistor on the base substrate is located within an orthographic projection of the first gate of the second transistor on the base substrate;
the first gate of the fourth transistor is located on a side of the channel region of the fourth transistor close to the base substrate; an orthographic projection of the second gate of the fourth transistor on the base substrate is located within an orthographic projection of the first gate of the fourth transistor on the base substrate.

6. The pixel driving circuit according to claim 3 , wherein the driving transistor comprises a first electrode configured to load a first power supply voltage, a second electrode connected to the third node and a gate connected to the first node;
the data writing circuit comprises:
a first transistor comprising a first electrode configured to load the data voltage, a second electrode connected to the second node, and a gate configured to load the first scan signal;
the light emitting control circuit comprises:
a seventh transistor comprising a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate configured to load the light emitting control signal;
the first reset circuit comprises:
a fifth transistor comprising a first electrode configured to load the reference voltage, a gate configured to load the first reset signal, and a second electrode connected to the second node;
a sixth transistor comprising a first electrode configured to load the reference voltage, a gate configured to load the light emitting control signal, and a second electrode connected to the second node;
the third reset circuit comprises:
an eighth transistor comprising a first electrode configured to load the initialization voltage, a gate configured to load the first reset signal, and a second electrode connected to the fourth node.

7. The pixel driving circuit according to claim 6 , wherein each of active layers of the first transistor, the driving transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor comprises a channel region, a first electrode and a second electrode located on both sides of the channel region, and materials of the active layers are all polysilicon semiconductor materials.

8. The pixel driving circuit according to claim 6 , wherein the pixel driving circuit is arranged on a side of a base substrate of a display panel;
the display panel comprises a data lead and a first power supply voltage lead extending along a column direction, the data lead is connected to the first electrode of the first transistor, and the first power supply voltage lead is electrically connected to the first electrode of the driving transistor;
the pixel driving circuit comprises a first metal wiring structure electrically connected to the first power supply voltage lead and insulated from the data lead; an orthographic projection of the data lead on the base substrate at least partially overlaps with an orthographic projection of the first metal wiring structure on the base substrate.

9. The pixel driving circuit according to claim 8 , wherein the pixel driving circuit further comprises a second metal wiring structure connecting the second electrode of the fifth transistor and the second electrode of the sixth transistor;
an orthographic projection of the second

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Li
• Feng Yu
• Zhang Hao

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title