Display panel and display device

Patent metadata

Field	Value
Publication number	US-12300133-B2
Application number	US-202117921486-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Nov 29, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

The display panel includes an active area and a border-frame area located at a periphery of the active area, the active area includes a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels, and the border-frame area includes a testing area and a bonding area; the testing area includes a plurality of testing units that are arranged periodically in a first direction, each of the testing units includes one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signal lead wire, and a second electrode is connected to one of the data lines; the bonding area includes a plurality of bonding units that are arranged periodically in the first direction, each of the bonding units includes one or more bonding pads, and each of the bonding pads is connected to one of the data lines.

First claim

The invention claimed is:

1. A display panel, wherein the display panel comprises an active area and a border-frame area located at a periphery of the active area, the active area comprises a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels, and the border-frame area comprises a testing area and a bonding area;
the testing area comprises a plurality of testing units that are arranged periodically in a first direction, each of the testing units comprises one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signal lead wire, the testing-signal lead wire is configured to transmit a testing signal, and a second electrode of the switching transistor is connected to one of the data lines;
the bonding area comprises a plurality of bonding units that are arranged periodically in the first direction, each of the bonding units comprises one or more bonding pads, and each of the bonding pads is connected to one of the data lines; and
in the first direction, a ratio of a quantity of the switching transistors comprised in one arrangement period of the testing units to a quantity of the bonding pads comprised in one arrangement period of the bonding units is greater than 0 and less than 2;
wherein the border-frame area further comprises an inputting area, the inputting area is located on one side of the testing area that is away from the active area, the inputting area comprises a plurality of testing-signal bus lines, and an extending direction of the testing-signal bus lines intersects with an extending direction of the testing-signal lead wires; and
the testing-signal bus lines are connected to the testing-signal lead wires, and the testing-signal bus lines are configured to input a testing signal via the testing-signal lead wires to data lines of sub-pixels of a same color;
wherein the plurality of testing-signal bus lines comprise at least one internal transmission bus, and the internal transmission bus is located at a first metal layer;
the testing-signal lead wires are located at a second metal layer, and a first insulating layer is disposed between the first metal layer and the second metal layer;
a second insulating layer is disposed on one side of the second metal layer that is back away from the first metal layer, a first electrode layer is disposed on one side of the second insulating layer that is back away from the first metal layer, and the first electrode layer comprises a plurality of switching electrodes; or a third insulating layer is disposed on one side of the first metal layer that is back away from the second metal layer, a second electrode layer is disposed on one side of the third insulating layer that is back away from the second metal layer, and the second electrode layer comprises a plurality of switching electrodes;
the testing-signal lead wires and the internal transmission bus are connected by the switching electrodes; and
a first part of each of the switching electrodes is connected to one of the testing-signal lead wires by a first via hole, and a second part of the switching electrode is connected to the internal transmission bus by a second via hole.

2. The display panel according to claim 1 , wherein within the testing area, all of the testing-signal lead wires and the data lines extend in a second direction, wherein the second direction is perpendicular to the first direction; and
a part of the testing-signal lead wire is further used as the first electrode of the switching transistor, and a part of the data line is further used as the second electrode of the switching transistor.

3. The display panel according to claim 1 , wherein each of the testing units comprises a plurality of switching transistors;
within the testing unit, all of first electrodes of the switching transistors are located on same sides of second electrodes of the switching transistor, and orthographic projections of the switching transistors in a second direction do not intersect or overlap with each other, wherein the second direction is perpendicular to the first direction; and
the plurality of switching transistors comprise a first transistor and a second transistor, and an orthographic projection of a second electrode of the first transistor and an orthographic projection of a first electrode of the second transistor in the first direction intersect or overlap.

4. The display panel according to claim 3 , wherein within the testing unit, the plurality of switching transistors further comprise a third transistor, the third transistor is close to the second transistor, and an orthographic projection of the second electrode of the second transistor and an orthographic projection of a first electrode of the third transistor in the first direction intersect or overlap.

5. The display panel according to claim 1 , wherein the testing area and the bonding area are located on two opposite sides of the active area.

6. The display panel according to claim 1 , wherein the testing area and the bonding area are located on a same one side of the active area, and the bonding area is located between the active area and the testing area.

7. The display panel according to claim 6 , wherein the data lines comprise data transmission lines and data inputting lines, two ends of each of the data transmission lines are connected to the second electrode of the switching transistor and a first end of the bonding pad, and a second end of the bonding pad is connected to one of the data inputting lines.

8. The display panel according to claim 1 , wherein each of the switching transistors comprises a channel area, and a width-length ratio of the channel area is greater than or equal to 13/3, and less than or equal to 200/4.

9. The display panel according to claim 1 , wherein an orthographic projection of the first via hole on a plane where the testing-signal lead wire is located is located within an area of the testing-signal lead wire.

10. The display panel according to claim 1 , wherein the at least one internal transmission bus comprises a first internal bus and a second internal bus, and the first internal bus is located on one side of the second internal bus that is close to the active area;
an arranging direction of a first via hole and a second via hole that connect the testing-signal lead wire and the first internal bus is perpendicular to an extending direction of the first internal bus; and
an arranging direction of a first via hole and a second via hole that connect the testing-signal lead wire and the second internal bus is parallel to an extending direction of the second internal bus.

11. The display panel according to claim 1 , wherein the plurality of testing-signal bus lines further comprise an edge transmission bus, the edge transmission bus is located on one side of the at least one internal transmission bus that is away from the active area, the edge transmission bus is located at the second metal layer, and the edge transmission bus and the testing-signal lead wires that are interconnected are of an integral structure.

12. A display panel, wherein the display panel comprises an active area and a border-frame area located at a periphery of the active area, the active area comprises a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels, and the border-frame area comprises a testing area and a bonding area;
the testing area comprises a plurality of testing units that are arranged periodically in a first direction, each of the testing units comprises one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signa

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Desheng
• Yang Zhichao
• Zhang Yong
• Wang Jian
• Nie Lingfang
• Hao Longhu
• An Yashuai
• Wang Peipei
• Guo Zanwu
• Yu Zhaohu
• Qu Feng
• Yin Xiaofeng
• Pang Jing
• Deng Qi

Classifications

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3607

  for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels (display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127) · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136254

  Checking; Testing · CPC title