Systems and methods of estimating thermal properties of semiconductor devices

Patent metadata

Field	Value
Publication number	US-12299369-B2
Application number	US-202217669652-A
Country	US
Kind code	B2
Filing date	Feb 11, 2022
Priority date	Oct 18, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

First claim

What is claimed is:

1. A method for analyzing an integrated circuit, comprising:
receiving, by a thermal analysis tool, a layout configured for physically forming an integrated circuit;
identifying, by the thermal analysis tool, at least a first net and at least a second net of the formed integrated circuit, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction;
dividing, by the thermal analysis tool, the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units;
estimating, by the thermal analysis tool, a first thermal conductivity of each of the first subsets of grid units;
estimating, by the thermal analysis tool, a second thermal conductivity of each of the second subsets of grid units; and
estimating, by the thermal analysis tool, an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

2. The method of claim 1 , wherein the first net originates from a first heat source, travels through one or more first interconnect structures of the integrated circuit, and ends at one of a plurality of bonding structures of the integrated circuit, and wherein the second net originates from a second heat source, travels through one or more second interconnect structures of the integrated circuit, and ends at a dielectric structure of the integrated circuit.

3. The method of claim 2 , wherein the first and second heat sources are disposed along a surface of a substrate of the integrated circuit.

4. The method of claim 3 , wherein the plurality of bonding structures are disposed away from the substrate with a first distance along the vertical direction, and the one or more second interconnect structures are disposed away from the substrate with a second distance, the first distance being substantially greater than the second distance.

5. The method of claim 1 , wherein a first size of one of the first subset of grid units is substantially smaller than a second size of one of the second subset of grid units.

6. The method of claim 1 , wherein the first net serves as at least one of a power net or an input/output net.

7. The method of claim 1 , wherein the second net serves as a signal net.

8. The method of claim 1 , wherein each of the first subset of grid units includes at least a portion of one of a plurality of interconnect structures of the integrated circuit, the plurality of interconnect structures essentially consisting of a metal material.

9. The method of claim 1 , wherein each of the second subset of grid units includes at least a portion of a interlayer disposed between adjacent ones of a plurality of interconnect structures of the integrated circuit, the interlayer essentially consisting of a dielectric material.

10. The method of claim 1 , wherein the step of estimating the first thermal conductivity of each of the first subsets of grid units further comprises:
calculating, by the thermal analysis tool, a respective metal density of each of the first subset of grid units; and
multiplying, by the thermal analysis tool, the metal density by a thermal conductivity of a bulk metal material to estimate the first thermal conductivity.

11. The method of claim 1 , wherein the step of estimating the second thermal conductivity of each of the second subsets of grid units further comprises:
identifying, by the thermal analysis tool, a respective type of each of the second subset of grid units to determine the second thermal conductivity, wherein the type includes: a first type, essentially consisting of a first dielectric material, that is associated with a lowest combined thermal conductivity; a second type, including a half of a second dielectric material and a half of a first metal material, that is associated with a medium combined thermal conductivity; and a third type, essentially consisting of a second metal material, that is associated with a highest combined thermal conductivity.

12. A automation system, comprising:
at least one processor; and
at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to:
group a plurality of nets of an integrated circuit into a first category and a second category, wherein the integrated circuit is physically formed based on a layout, and wherein the first category includes a plurality of first nets and the second category includes a plurality of second nets each extending through the formed integrated circuit;
construct each of the plurality of first nets with a plurality of first grid units;
construct each of the plurality of second nets with a plurality of second grid units, wherein a second size of the plurality of second grid units is different from a first size of the plurality of first grid units;
estimate first thermal conductivities of the plurality of first grid units, respectively, based on the first size;
estimate second thermal conductivities of the plurality of second grid units, respectively, based on the second size; and
estimate an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivities and the second thermal conductivities.

13. The system of claim 12 , wherein each of the plurality of first nets in the first category operatively serves as a portion of a power net or a portion of an input/output net, and each of the plurality of second nets in the second category operatively serves as a portion of a signal net.

14. The system of claim 12 , wherein the first size is substantially smaller than the second size.

15. The system of claim 12 , wherein the system is further caused to assign each of the plurality of first nets into the first category based on identifying that the corresponding first net travels through at least one bonding structure of the integrated circuit.

16. The system of claim 12 , wherein the system is further caused to assign each of the plurality of second nets into the second category based on identifying that the corresponding second net is not coupled to any bonding structure of the integrated circuit.

17. The system of claim 12 , wherein each of the plurality of first nets in the first category travels through at least one of the following structures of the integrated circuit: a power rail structure, an input/output pin structure, or a through-silicon-via structure.

18. A non-transitory computer readable medium comprising computer executable instructions for carrying out a method for analyzing an integrated circuit, the method comprising:
receiving a layout configured for physically forming an integrated circuit;
identifying a plurality of nets of the formed integrated circuit;
grouping the plurality of nets into a first category and a second category based on the layout of the integrated circuit, wherein the first category includes a plurality of first nets that each serve as a power net or an input/output net of the integrated circuit, and the second category includes a plurality of second nets that each serve as a signal net of the integrated circuit;
estimating respective first thermal conductivities of a plurality of first grid units disposed along the plurality of first nets;
estimating re

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Ching-Yi
• Chang Fong-Yuan
• Chen Po-Yu
• Huang Po-Hsiang
• Chang Chih-Wei
• Lee Jyh Chwen Frank

Classifications

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/23

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title