Continuous-time delta-sigma analog-to-digital converter and operation method thereof

Patent metadata

Field	Value
Publication number	US-12294388-B2
Application number	US-202318168882-A
Country	US
Kind code	B2
Filing date	Feb 14, 2023
Priority date	Feb 15, 2022
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Disclosed are a continuous-time delta-sigma analog-to-digital converter and an operation method thereof. More particularly, a continuous-time delta-sigma analog-to-digital converter, including: a linear integrator configured to generate a first output signal corresponding to a preset input voltage based on an operation of a linear Gm circuit that receives the preset input voltage; and a quantizer configured to generate a second output signal corresponding to the first output signal based on an operation of a body-driven VCO that receives the first output signal and to generate a digital output code corresponding to the second output signal based on an operation of a Frequency to Digital Converter (FDC) that receives the second output signal is disclosed.

First claim

What is claimed is:

1. A continuous-time delta-sigma analog-to-digital converter, comprising:
a linear integrator configured to generate a first output signal corresponding to a preset input voltage based on an operation of a linear Gm circuit that receives the preset input voltage; and
a quantizer configured to generate a second output signal corresponding to the first output signal based on an operation of a body-driven VCO that receives the first output signal and to generate a digital output code corresponding to the second output signal based on an operation of a Frequency to Digital Converter (FDC) that receives the second output signal,
wherein the continuous-time delta-sigma analog-to-digital converter operates based on an input impedance determined by chopping frequency (f CH ) at a node connected to an input terminal of the linear integrator and an input capacitor (C IN ) provided between the input terminal of the linear integrator and a ground line.

2. The continuous-time delta-sigma analog-to-digital converter according to claim 1 , wherein the linear Gm circuit comprises a plurality of operational amplifiers (OPAMP);
and a plurality of resistors respectively connected to input terminals of the OPAMPs.

3. The continuous-time delta-sigma analog-to-digital converter according to claim 2 , wherein the plural resistors are respectively connected to the OPAMPs through one side end of each of the plural resistors and are connected to a power supply voltage VDD line through another side end of each of the plural resistors.

4. The continuous-time delta-sigma analog-to-digital converter according to claim 2 , wherein the OPAMPs are current-recycling OPAMP.

5. The continuous-time delta-sigma analog-to-digital converter according to claim 2 , wherein, by the linear integrator, the input voltage is copied to both ends of the plural resistors by a unit gain feedback in the linear Gm circuit to generate a linearly changing current, and the first output signal that corresponds to a change in the generated current is generated.

6. The continuous-time delta-sigma analog-to-digital converter according to claim 1 , wherein the linear integrator further comprises a DC-current source connected to an output terminal of the linear Gm circuit.

7. The continuous-time delta-sigma analog-to-digital converter according to claim 1 , wherein the body-driven VCO comprises a plurality of inverter delay cells,
wherein the first output signal is received through a body terminal of each of the plural inverter delay cells.

8. The continuous-time delta-sigma analog-to-digital converter according to claim 7 , wherein each of the plural inverter delay cells comprises a PMOS transistor connected to a power supply voltage line; and an NMOS transistor connected to the PMOS transistor and a ground line, wherein the first output signal is received through a body terminal of each of the PMOS transistor and the NMOS transistor.

9. The continuous-time delta-sigma analog-to-digital converter according to claim 1 , further comprising a 4-tap FIR filter provided on a delta-sigma feedback loop that connects an input terminal of the linear integrator and an output terminal of the quantizer.

10. An operation method of a continuous-time delta-sigma analog-to-digital converter, the operation method comprising:
by a linear integrator, generating a first output signal corresponding to a preset input voltage based on an operation of a linear Gm circuit that receives the preset input voltage;
by a quantizer, generating a second output signal corresponding to the first output signal based on an operation of a body-driven VCO that receives the first output signal; and
by the quantizer, generating a digital output code corresponding to the second output signal based on an operation of a Frequency to Digital Converter (FDC) that receives the second output signal,
wherein the operation method of the continuous-time delta-sigma analog-to-digital converter operates based on an input impedance determined by chopping frequency (fCH) at a node connected to an input terminal of the linear integrator and an input capacitor (CIN) provided between the input terminal of the linear integrator and a ground line.

Assignees

• Daegu Gyeongbuk Inst Science & Tech

Inventors

• Lee Jung Hyup
• Choi Ji Woong
• Lee Se Hwan

Classifications

• H03M1/60

  with intermediate conversion to frequency of pulses · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/484 Primary

  by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path · CPC title

• H03M3/422 Primary

  having one quantiser only · CPC title