Single slope analogue to digital converter and operating method thereof

Patent metadata

Field	Value
Publication number	US-12294382-B2
Application number	US-202318161276-A
Country	US
Kind code	B2
Filing date	Jan 30, 2023
Priority date	Jan 30, 2023
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Disclosed herein is a method of operating a single slope analog-to-digital converter (ADC), which includes receiving an input signal from a sensor or a ramp signal from a ramp generator according to a state of a switch and sampling the received input or ramp signal, comparing, by a comparator, whether the sampled ramp signal is present in a predetermined input range in a state in which the ramp generator maintains an off state and outputting the comparison result, generating, by a logic part, a flag signal indicating a high or low according to the comparison result by the comparator and providing the flag signal to the ramp generator, and sampling, by the ramp generator, a reference voltage of the comparator according to the flag signal based on an off or on state.

First claim

What is claimed is:

1. A method of operating a single slope analog-to-digital converter (ADC), the method comprising:
receiving an input signal from a sensor or a ramp signal from a ramp generator according to a state of a switch and sampling the received input or ramp signal;
determining, by a comparator, whether the sampled ramp signal is present in a predetermined input range in a state in which the ramp generator maintains an off state and outputting a determination result;
generating, by a logic part, a flag signal indicating a high or low according to the determination result by the comparator and providing the flag signal to the ramp generator; and
sampling, by the ramp generator, a reference voltage of the comparator according to the flag signal based on an off or on state.

2. The method of claim 1 , wherein the generating of, by the logic part, the flag signal indicating the high or low according to the determination result by the comparator and the providing of the flag signal to the ramp generator includes generating a flag signal indicating a high and providing the flag signal to the ramp generator when the sampled ramp signal is present in the predetermined input range on the basis of the determination result by the comparator.

3. The method of claim 2 , wherein sampling, by the ramp generator, a reference voltage of the comparator according to the flag signal based on an off or on state includes maintaining the ramp generator in the on state when the flag signal indicates the high.

4. The method of claim 2 , wherein sampling, by the ramp generator, a reference voltage of the comparator according to the flag signal based on an off or on state includes maintaining the ramp generator in the off state when the flag signal indicates the low.

5. The method of claim 1 , wherein the generating of, by the logic part, the flag signal indicating the high or low according to the determination result by the comparator and the providing of the flag signal to the ramp generator includes generating a flag signal indicating a low and providing the flag signal to the ramp generator when the sampled ramp signal is present outside the predetermined input range on the basis of the determination result by the comparator.

6. A single slope analog-to-digital converter (ADC) comprising:
a switch configured to provide a path for receiving an input signal from a sensor and a path for receiving a ramp signal from a ramp generator;
a comparator configured to receive a sampled input signal or a sampled ramp signal according to a state of the switch, determine whether the sampled input signal is present in a predetermined input range in a state in which the ramp generator maintains an off state, and output a determination result;
a logic part configured to generate a flag signal indicating a high or low according to the determination result by the comparator; and
a ramp generator which maintains an off or on state according to the flag signal received from the logic part.

7. The single slope ADC of claim 6 , wherein the logic part generates a flag signal indicating a high and provides the flag signal to the ramp generator when the sampled ramp signal is present in the predetermined input range on the basis of the determination result by the comparator.

8. The single slope ADC of claim 7 , wherein the ramp generator maintains the on state when the flag signal indicates the high.

9. The single slope ADC of claim 6 , wherein the logic part generates a flag signal indicating a low and provides the flag signal to the ramp generator when the sampled ramp signal is present outside the predetermined input range on the basis of the determination result by the comparator.

10. The single slope ADC of claim 9 , wherein the ramp generator maintains the off state when the flag signal indicates the low.

Assignees

• Knu Industry Cooperation Found

Inventors

• Kim Hyeon Joon

Classifications

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M1/0675

  using redundancy · CPC title

• H03M1/125

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/56 Primary

  Input signal compared with linear ramp · CPC title