Dual-gain single-slope ADC with digital CDS

Patent metadata

Field	Value
Publication number	US-10205463-B1
Application number	US-201816039116-A
Country	US
Kind code	B1
Filing date	Jul 18, 2018
Priority date	Jul 18, 2018
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A column-parallel dual-gain single-slope ADC comprises an input for receiving a signal Vin, a sample-and-hold stage which receives Vin and outputs sampled signal Vin,samp, a comparator, a counter, and a ramp generator which generates high-gain (HG) and low-gain (LG) ramps, with the ratio of the LG ramp slope to the HG ramp slope being greater than 1. During a coarse conversion phase, Vin,samp is compared with a threshold voltage Vthresh, and a flag is set to a first or second state depending on the comparison. During a fine conversion phase, if the flag is in the first state, the HG ramp is provided to the comparator and its output toggles when the ramp voltage becomes equal to Vin,samp. If the flag is in the second state, the LG ramp is provided to the comparator and its output toggles when the LG ramp voltage becomes equal to Vin,samp.

First claim

We claim:

1. A column-parallel dual-gain single-slope analog-to-digital converter (ADC), said ADC comprising:
an input node for receiving an input signal V in , said input signal V in having an associated maximum input swing ΔV in,max ;
a sample-and-hold (S/H) stage having an input coupled to said input node and arranged to sample V in and provide sampled signal V in,samp at an S/H output;
a comparator having first and second inputs and an output;
a threshold voltage V thresh ;
a counter, which steps through a predefined range of count values in a count time;
a global ramp generator, that is common to multiple ADC columns and generates a high-gain (HG) ramp and a low-gain (LG) ramp, such that:
said HG and LG ramps ramp up or down simultaneously;
the ratio G of said LG ramp slope to said HG ramp slope is G>1;
the swing of said LG ramp during said count time is ΔV ramp,LG ≥ΔV in,max ;
the swing of said HG ramp during said count time is ΔV ramp,HG =ΔV ramp,LG /G;

said ADC arranged such that:
during a sampling phase, input signal V in is sampled by said S/H stage and the sampled voltage V in,samp is provided to said comparator's first input;
during a coarse conversion phase, V in,samp is compared with V thresh and a flag hg_flag is set to either a first state or a second state depending on the comparison;
during a fine conversion phase, which follows said coarse conversion phase and includes said count time,
if said hg_flag is in said first state, said HG ramp is provided to said comparator's second input and said comparator output toggles when the HG ramp voltage becomes equal to V in,samp , and
if said hg_flag is in said second state, said LG ramp is provided to said comparator's second input and said comparator output toggles when the LG ramp voltage becomes equal to V in,samp .

2. The ADC of claim 1 , wherein said sampling phase occurs simultaneously with said coarse and fine conversion phases.

3. The ADC of claim 1 , further arranged such that:
said input signal V in varies between a constant reset level V rst and a signal level V sig =V rst −ΔV sig , where ΔV sig is signal amplitude, which is either positive or negative depending on the application;
during said count time said LG ramp swings from V ramp,LG,start to V ramp,LG,end =V ramp,LG,start −ΔV ramp,LG , where ΔV ramp,LG has the same polarity as ΔV sig , and V rst and V sig are between V ramp,LG,start and V ramp,LG,end ;
during said count time said HG ramp swings from V ramp,HG,start to V ramp,HG,end =V ramp,HG,start −ΔV ramp,HG , where ΔV ramp,HG has the same polarity as ΔV sig , and V rst is between V ramp,HG,start and V ramp,HG,end ;
said threshold voltage V thresh =V ramp,HG,end +ΔV, where ΔV has the same polarity as ΔV sig and 0<|ΔV|<|ΔV ramp,HG |;
if ΔV sig >0, said hg_flag is in said first state if V in,samp >V thresh , and said hg_flag is in said second state if V in,samp ≤V thresh ;
if ΔV sig <0, said hg_flag is in said first state if V in,samp <V thresh , and said hg_flag is in said second state if V in,samp ≥V thresh .

4. The ADC of claim 3 , wherein said input signal V in is equal to said reset level V rst during a first “reset read” portion of a row time, and said input signal V in is equal to said signal level V sig during a second “signal read” portion of said row time.

5. The ADC of claim 4 , said ADC operated to perform two conversions per row time and further arranged such that:
the ADC digitizes said signal level V sig (signal conversion) and then said reset level V rst (reset conversion) in this order within said row time thereby performing digital correlated double sampling (CDS);
said coarse conversion phase is present during said signal conversion and is not present during said reset conversion;
the state of said hg_flag is established during said signal conversion and the same value is used during said reset conversion.

6. The ADC of claim 4 , said ADC operated to perform one conversion per row time and further arranged such that:
said reset read precedes said signal read;
said sampling phase occurs during said signal read; and
the ADC digitizes said signal level V sig .

7. The ADC of claim 5 , wherein said reset read precedes said signal read.

8. The ADC of claim 1 , wherein:
said counter is an n-bit counter,
the ADC quantization step is ΔV ramp,LG /2 n and the ADC resolution is n when said hg_flag is in said second state,
the ADC quantization step is ΔV ramp,LG /(G·2 n ) and the ADC resolution is n+log 2 G when said hg_flag is in said first state.

9. The ADC of claim 1 , wherein G is a power of 2.

10. The ADC of claim 5 , said ADC further arranged such that:
said input signal V in is a pixel output having an associated pixel reset level and pixel signal level, said pixel reset level being the pixel output with no integrated photocurrent and said pixel signal level being the pixel output with integrated photocurrent;
said reset level V rst is equal to said pixel reset level; and
said signal level V sig is equal to said pixel signal level.

11. The ADC of claim 1 , further comprising digital memory, said ADC arranged such that the value of said counter is latched and stored in said digital memory when said comparator output toggles during said fine conversion phase.

12. The ADC of claim 11 , wherein said ADC is arranged to provide an output consisting of the counter value stored in said digital memory and the state of said hg_flag.

13. The ADC of claim 1 , further comprising a multiplexer having at least three inputs and an output, said voltage V thresh , said HG ramp, and said LG ramp provided to respective multiplexer inputs and said output coupled to said comparator's second input, said ADC arranged to operate said multiplexer such that V thresh is selected and thereby connected to said multiplexer output during said coarse conversion phase, said HG ramp is selected and thereby connected to said multiplexer output during said fine conversion phase if said hg_flag is in said first state, and said LG ramp is selected and thereby connected to said multiplexer output during said fine conversion phase if said hg_flag is in said second state.

14. The ADC of claim 13 , wherein said multiplexer comprises a local ramp buffer interposed between its inputs and its output.

15. The ADC of claim 14 , wherein said local ramp buffer is a source follower.

16. The ADC of claim 1 , further comprising an analog CDS stage interposed between said ADC input node and the input to said S/H stage.

17. The ADC of claim 16 , wherein said analog CDS stage comprises:
a capacitor connected in series between said CDS input and a first node;
a clamp switch connected between said first node and a fixed voltage V clamp ; and
a buffer connected between said first node and said CDS output;
said analog CDS stage further arranged such that:
said clamp switch is closed during said reset read and the voltage at said CDS input is equal to a voltage V in1 ,
said clamp switch is open during said signal read and the voltage at said CDS input is equal to a voltage V in2 ,
said reset level V rst is substantially equal to said fixed voltage V clamp , and
said signal amplitude ΔV sig is substantially equal to (V in1 −V in2 ).

18. The ADC of claim 17 , said ADC further arranged such that:
said CDS input is a pixel output having an associated pixel reset level and pixel signal level, said pixel reset level being the pixel output with no integrated photocurrent and said pixel signal level being the pixel output with integrate

Assignees

• Teledyne Scient & Imaging Llc

Inventors

• Milkov Mihail
• Lafevre Kyle

Classifications

• H03M1/0854

  of quantisation noise · CPC title

• H03M1/0675

  using redundancy · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M1/56 Primary

  Input signal compared with linear ramp · CPC title

• H03M1/1295

  Clamping, i.e. adjusting the DC level of the input signal to a predetermined value · CPC title