Low power crystal oscillator with automatic amplitude control

US12294372B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12294372-B2
Application numberUS-202318323998-A
CountryUS
Kind codeB2
Filing dateMay 25, 2023
Priority dateJun 8, 2022
Publication dateMay 6, 2025
Grant dateMay 6, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

First claim

Opening claim text (preview).

The invention claimed is: 1. A low power crystal oscillator circuit, comprising: a crystal; a high power supply; a low power supply; a first capacitor having a first terminal coupled to the crystal; a second capacitor having a first terminal coupled to the crystal; a first current mirror transistor having a first terminal coupled to the high power supply, and a second terminal coupled to a gate terminal, the first current mirror transistor having a channel with a first width to length ratio; a first current source configured to output a current of a first value, the first current source having a first terminal coupled to the second terminal of the first current mirror transistor; a second current mirror transistor having a first terminal coupled to the high power supply, a gate terminal coupled to the gate terminal of the first current mirror transistor, a second terminal coupled to the crystal, and the second current mirror transistor having a second width to length ratio that is X times greater than the first width to length ratio; a third current mirror transistor having a first terminal coupled to the high power supply and a second terminal coupled to a gate terminal of the third current mirror transistor, the third current mirror transistor having a third width to length ratio; a second current source configured to output a current of a second value, the second current source having a first terminal coupled to the second terminal of the third current mirror transistor; a fourth current mirror transistor having a first terminal coupled to the high power supply, a gate terminal coupled to the gate terminal of the third current mirror transistor, and a second terminal coupled to the second terminal of the second current mirror transistor, the fourth current mirror transistor having a fourth width to length ratio that is Y times greater than the third width to length ratio; and a fifth current mirror transistor having a first terminal coupled to the high power supply, a gate terminal coupled to the gate terminals of the third current mirror transistor and the fourth current mirror transistor, and a second terminal coupled to the second terminal of the first current mirror transistor, the fifth current mirror transistor having a fifth width to length ratio that is Z times smaller than the third width to length ratio, the gate terminals of the third current mirror transistor, the fourth current mirror transistor, and the fifth current mirror transistor are coupled to the crystal. 2. The low power crystal oscillator circuit of claim 1 , further comprising: a third capacitor having a first terminal coupled to an input terminal of the crystal and a second terminal coupled to the gate terminals of the third current mirror transistor, the fourth current mirror transistor, and the fifth current mirror transistor, the first capacitor having a second terminal coupled to the low power supply, the second capacitor having a second terminal coupled to the low power supply, the current of the second value being less than the current of the first value, the first current source having a second terminal coupled to the low power supply, the second current source having a second terminal coupled to the low power supply. 3. The low power crystal oscillator circuit of claim 1 , further comprising: a current limiting circuit coupled between the high power supply and the first terminal of the fourth current mirror transistor, the current limiting circuit limiting current that flows from the high power supply to the first terminal of the fourth current mirror transistor to a third value, the current of the third value being less than the current of the first value. 4. The low power crystal oscillator circuit of claim 1 wherein X is greater than 200. 5. The low power crystal oscillator circuit of claim 1 wherein Y is greater than 2. 6. The low power crystal oscillator circuit of claim 5 wherein Z is greater than 3. 7. A low power crystal oscillator circuit, comprising a crystal having an input terminal and an output terminal; a high power supply; a low power supply; a first capacitor coupled to the input terminal of the crystal; a second capacitor coupled to the output terminal of the crystal; a first current mirror transistor coupled to the high power supply; a first current source configured to output a current of a first value, the first current source coupled to the first current mirror transistor; a second current mirror transistor coupled to the high power supply and the first current mirror transistor; a third current mirror transistor coupled to the high power supply; a second current source configured to output a current of a second value less than the first value, the second current source coupled to the third current mirror transistor; a fourth current mirror transistor coupled to the third current mirror transistor and the second current mirror transistor; a fifth current mirror transistor coupled to the high power supply, the third current mirror transistor, the fourth current mirror transistor, and first current mirror transistor; and a third capacitor coupled to the input terminal of the crystal and coupled to gate terminals of the third current mirror transistor, the fourth current mirror transistor, and the fifth current mirror transistor, the gate terminals of the third current mirror transistor, the fourth current mirror transistor, and the fifth current mirror transistor are coupled to the input terminal of the crystal; and a sixth current mirror transistor coupled to the high power supply; a third current source outputting current of a third value that is less than the first value, the third current source coupled to the sixth current mirror transistor; and a seventh current mirror transistor coupled to the high power supply, a gate terminal coupled to a gate terminal of the sixth current mirror transistor, and a second terminal coupled to a first terminal of the fourth current mirror transistor. 8. The low power crystal oscillator circuit of claim 7 wherein a width to length ratio of the second current mirror transistor is greater than a width to length ratio of the first current mirror transistor. 9. The low power crystal oscillator circuit of claim 7 wherein a width to length ratio of the fourth current mirror transistor is greater than a width to length ratio of the third current mirror transistor. 10. The low power crystal oscillator circuit of claim 9 wherein a width to length ratio of the second current mirror transistor is less than the width to length ratio of the third current mirror transistor. 11. The low power crystal oscillator circuit of claim 9 , further comprising: a fourth capacitor having a first terminal coupled to the gate terminal of the sixth current mirror transistor and a second terminal coupled to the high power supply. 12. The low power crystal oscillator circuit of claim 7 wherein the second value is equal to the third value. 13. A low power crystal oscillator circuit, comprising: a crystal; a high power supply; a low power supply; a first capacitor coupled between the crystal and the low power supply; a second capacitor coupled between the crystal and the low power supply; a first current mirror transistor coupled to the high power supply; a first current source of a first value coupled to the first current mirror transistor; a second current mirror transistor coupled to the high power supply and to the first current mirror transistor; a third current mirror transistor coupled to the high power supply and the first current mirror transistor; a second current source of a se

Assignees

Inventors

Classifications

  • Modifications of generator to improve response time or to decrease power consumption · CPC title

  • Stabilisation of output, e.g. using crystal · CPC title

  • including a current mirror · CPC title

  • the amplifier comprising field effect transistors (H03B5/366 takes precedence) · CPC title

  • H03K3/0307Primary

    Stabilisation of output, e.g. using crystal · CPC title

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Frequently asked questions

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What does patent US12294372B2 cover?
A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to furt…
Who is the assignee on this patent?
St Microelectronics Int Nv
What technology area does this patent fall under?
Primary CPC classification H03K3/0307. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 06 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).