Driving method of liquid crystal display panel and liquid crystal display panel

Patent metadata

Field	Value
Publication number	US-12293735-B2
Application number	US-202218577838-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Aug 25, 2022
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A liquid crystal display panel and a driving method of a liquid crystal display panel. The driving method includes: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels among the plurality of rows of sub-pixels, in which the first gate signal includes an on period and an off period used to control the first row of sub-pixels to be turned on and off respectively; writing, during the on period of the first gate signal, a plurality of first data signals to sub-pixels among the first row of sub-pixels through the plurality of data lines, and during the on period of the first gate signal, a first writing time length of a negative polarity data signal is less than a second writing time length of a positive polarity data signal.

First claim

The invention claimed is:

1. A driving method of a liquid crystal display panel, wherein the liquid crystal display panel comprises a pixel array, the pixel array comprises a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels, the plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns, each of the plurality of gate lines provides a gate signal for at least one row of sub-pixels, each of the plurality of data lines provides a data signal for at least one column of sub-pixels, each sub-pixel is connected with a corresponding gate line and a corresponding data line, and
the driving method comprises:
providing a first gate signal to a first gate line corresponding to a first row of sub-pixels among the plurality of rows of sub-pixels, wherein the first gate signal comprises an on period and an off period used to control the first row of sub-pixels to be turned on and off respectively;
writing, during the on period of the first gate signal, a plurality of first data signals to sub-pixels among the first row of sub-pixels through the plurality of data lines, wherein the plurality of first data signals comprise a positive polarity data signal and a negative polarity data signal, and
during the on period of the first gate signal, a first writing time length of the negative polarity data signal is less than a second writing time length of the positive polarity data signal;
wherein a delay time of the negative polarity data signal relative to a starting time point of the on period corresponding to the first gate signal is a first time length,
a delay time of the positive polarity data signal relative to the starting time point of the on period corresponding to the first gate signal is a second time length, and
the first time length is greater than the second time length, so that the first writing time length of the negative polarity data signal is less than the second writing time length of the positive polarity data signal during the on period of the first gate signal.

2. The driving method according to claim 1 , wherein each of the plurality of data lines provides data signals for two adjacent columns of sub-pixels,
during the on period of the first gate signal, each of the plurality of data lines provides a positive polarity data signal and a negative polarity data signal for a first sub-pixel and a second sub-pixel located in a same row and in two adjacent columns, respectively,
the on period of the first gate signal comprises a first sub-on period and a second sub-on period,
the positive polarity data signal is applied to the first sub-pixel during the first sub-on period, the negative polarity data signal is applied to the second sub-pixel during the second sub-on period, and
a time length of the first sub-on period is greater than a time length of the second sub-on period.

3. The driving method according to claim 2 , wherein each of the plurality of sub-pixels comprises a pixel electrode, and each of the plurality of data lines provides the positive polarity data signal to the pixel electrode of the first sub-pixel through a first multiplexing toggle switching element, and provides the negative polarity data signal to the pixel electrode of the second sub-pixel through a second multiplexing toggle switching element.

4. The driving method according to claim 3 , wherein the first multiplexing toggle switching element is connected with a first control line to receive a first control signal provided by the first control line, the first multiplexing toggle switching element is configured to be turned on and off in response to a control of the first control signal, the second multiplexing toggle switching element is connected with a second control line to receive a second control signal provided by the second control line, and the second multiplexing toggle switching element is configured to be turned on and off in response to a control of the second control signal.

5. The driving method according to claim 4 , wherein the first sub-on period and the second sub-on period are the same as an on period of the first multiplexing toggle switching element and an on period of the second multiplexing toggle switching element, respectively.

6. The driving method according to claim 5 , wherein the first multiplexing toggle switching element and the second multiplexing toggle switching element are disposed at a periphery of the liquid crystal display panel,
one column of sub-pixels in which the first sub-pixel is located share the first multiplexing toggle switching element, and
one column of sub-pixels in which the second sub-pixel is located share the second multiplexing toggle switching element.

7. The driving method according to claim 3 , wherein the first multiplexing toggle switching element is disposed in the first sub-pixel, and the second multiplexing toggle switching element is disposed in the second sub-pixel.

8. The driving method according to claim 7 , wherein each of the plurality of sub-pixels further comprises a pixel switching element, the pixel switching element is connected with a corresponding gate line to receive a gate signal provided by the corresponding gate line,
the pixel switching element and the first multiplexing toggle switching element in the first sub-pixel are connected in series between the data line and the pixel electrode, and the pixel switching element and the second multiplexing toggle switching element in the second sub-pixel are connected in series between the data line and the pixel electrode.

9. The driving method according to claim 3 , wherein the first multiplexing toggle switching element and the second multiplexing toggle switching element are disposed at a periphery of the liquid crystal display panel, one column of sub-pixels in which the first sub-pixel is located share the first multiplexing toggle switching element, and one column of sub-pixels in which the second sub-pixel is located share the second multiplexing toggle switching element.

10. The driving method according to claim 1 , wherein the starting time point of the on period corresponding to the first gate signal relative to the negative polarity data signal and the starting time point of the on period corresponding to the first gate signal relative to the positive polarity data signal are the same or different.

11. The driving method according to claim 10 , wherein the first gate signal further comprises a transition period between the on period and the off period adjacent to each other,
the first time length is greater than the second time length by a preset time length, and
the preset time length is a difference between a writing time length of the negative polarity data signal and a writing time length of the positive polarity data signal during the transition period of the first gate signal.

12. The driving method according to claim 1 , wherein the first gate signal further comprises a transition period between the on period and the off period adjacent to each other,
the first time length is greater than the second time length by a preset time length, and
the preset time length is a difference between a writing time length of the negative polarity data signal and a writing time length of the positive polarity data signal during the transition period of the first gate signal.

13. The driving method according to claim 1 , wherein each of the plurality of data lines provides data signals for two adjacent columns of sub-pixels,
during the on period of the first gate signal, each of the plurality of data lines provides a positive polarity data signal and a negative polarity data signal for a firs

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Weng Zuwei
• Lai Yichiang
• Hu Bo

Classifications

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3688 Primary

  suitable for active matrices only · CPC title