Method for charging pixels and display panel

Patent metadata

Field	Value
Publication number	US-11189241-B2
Application number	US-202016769401-A
Country	US
Kind code	B2
Filing date	Apr 10, 2020
Priority date	Mar 27, 2020
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A method for charging pixels and a display panel is provided, the method comprising: turning on thin-film transistor switches of pixels in a current row; inputting a positive polarity signal to one of a first data line and a second data line; inputting a negative polarity signal to the other of the first data line and the second data line at set intervals; turning off the thin-film transistor switches of the pixels in the current row.

First claim

What is claimed is:

1. A method for charging pixels of a display panel, wherein the display panel comprises a plurality of rows of scan lines and a plurality of columns of first data lines and second data lines, the first data lines and the second data lines are disposed alternately, any two adjacent first and second data lines and any two adjacent scan lines define a pixel, the pixels in any two adjacent rows are separated by only one of the scan lines, the pixels in any two adjacent columns are separated by only one of the first data lines or one of the second data lines, each pixel is provided with only one thin film transistor switch, and the method comprises:
turning on thin-film transistor switches of the pixels in a current row;
inputting a positive polarity signal to the first data lines in a picture frame;
inputting a negative polarity signal to the second data lines at a set interval in the same picture frame, so that a phase of the positive polarity signal and a phase of the negative polarity signal compensate each other in the same picture frame; and
turning off the thin-film transistor switches of the pixels arranged in the current row, which comprises:
pausing or stopping a gate signal being sent to the pixels in the current row;
delaying the turning off of the thin film transistor switches corresponding to the first data lines that are input the positive polarity signal by a first interval; and
delaying the turning off of the thin film transistor switches corresponding to the second data lines that are input the negative polarity signal by a second interval, wherein the second interval is greater than the first interval, and the set interval equals to a first time difference between the first interval and the second interval.

2. The method of claim 1 , wherein, before the step of turning on the thin-film transistor switches of the pixels in the current row, the method further comprises:
determining a polarity of a voltage signal to be input to each of the first data lines and the second data lines according to an (n)th picture frame, layout of the pixels in the display panel, or a polarity inversion of each pixel in an (n−1)th picture frame, where n is a positive integer.

3. The method of claim 1 , wherein the thin film transistor switches are P-type transistor switches or N-type transistor switches.

4. The method of claim 1 , wherein, before the step of turning on the thin-film transistor switches of the pixels in the current row, the method further comprises:
acquiring a second time difference between an off time of the thin film transistor switches corresponding to the first data lines that are input the positive polarity signal and an off time of the thin film transistor switches corresponding to the second data lines that are input the negative polarity signal in the same picture frame, wherein the set interval equals to the second time difference.

5. The method of claim 4 , wherein the second time difference ranges between 0.5 microseconds and 1 microsecond.

6. A display panel, comprising:
a plurality of rows of scan lines;
a plurality of columns of first data lines and second data lines that are disposed alternately, wherein any two adjacent first and second data lines and any two adjacent scan lines define a pixel, the pixels in any two adjacent rows are separated by only one of the scan lines, the pixels in any two adjacent columns are separated by only one of the first data lines or one of the second data lines;
a plurality of thin film transistor switches, wherein each pixel is provided with only one of the thin film transistor switches;
a gate driving circuit unit configured to turn on and off the thin film transistor switches of the pixels in a current row;
a first charging module configured to input a positive polarity signal to the first data lines in a picture frame;
a second charging module configured to input a negative polarity signal to the second data lines at a set interval in the same picture frame, so that a phase of the positive polarity signal and a phase of the negative polarity signal compensate each other in the same picture frame; and
a preset module configured to store and set the set interval, wherein the set interval equals to a time difference between an off time of the thin film transistor switches corresponding to the data lines that are input the positive polarity signal and an off time of the thin film transistor switches corresponding to the data lines that are input the negative polarity signal in the same picture frame.

7. The display panel of claim 6 , wherein the set interval ranges between 0.5 microseconds and 1 microsecond.

8. The display panel of claim 6 , further comprising:
a determination module configured to determine a polarity of a voltage signal to be input to each of the first data lines and the second data lines, according to an (n)th picture frame, layout of the pixels in the display panel, or a polarity inversion of each pixel in an (n−1)th picture frame, where n is a positive integer.

9. The display panel of claim 6 , wherein the display panel display is driven by a driving mode of a row inversion, a column inversion, a pixel inversion, or a half-frame inversion.

10. The display panel of claim 6 , wherein the gate driving circuit unit is configured to turn off the thin film transistor switches of the pixels in a current row by pausing or stopping sending a gate signal to the pixels in the current row;
when the gate driving circuit unit pauses or stops sending a gate signal to the pixels in the current row, the thin film transistor switches corresponding to the first data lines are turned off after a first interval, and the thin film transistor switches corresponding to the second data lines are turned off after a second interval; and
the second interval is greater than the first interval, and the set interval equals to a time difference between the first interval and the second interval.

Assignees

• Tcl China Star Optoelectronics Tech Co Ltd

Inventors

• Gao Xiang

Classifications

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3614 Primary

  Control of polarity reversal in general · CPC title