Pixel circuit and driving method therefor, display panel, and display apparatus

Patent metadata

Field	Value
Publication number	US-12293702-B2
Application number	US-202318358706-A
Country	US
Kind code	B2
Filing date	Jul 25, 2023
Priority date	Jun 14, 2022
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A pixel circuit includes a plurality of driving transistors and a plurality of gating sub-circuits. The plurality of driving transistors are configured to output different driving currents under control of a received control signal. Each gating sub-circuit is electrically connected to a respective selection signal terminal, a scanning signal terminal, a respective driving transistor and a light-emitting device, and is configured to be turned on under control of a scanning signal from the scanning signal terminal and a selection signal from the selection signal terminal to transmit a driving current from the connected driving transistor to the light-emitting device. Within a frame period, one of a plurality of selection signal terminals respectively electrically connected to the plurality of gating sub-circuits outputs a selection signal.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a plurality of driving transistors, wherein the plurality of driving transistors are configured to output different driving currents under control of a received control signal;
a plurality of gating sub-circuits, wherein each gating sub-circuit is electrically connected to a respective selection signal terminal, a scanning signal terminal, a respective driving transistor and a light-emitting device node; the light-emitting device node is configured to be electrically connected to a light-emitting device, and the gating sub-circuit is configured to be turned on under control of a scanning signal from the scanning signal terminal and a selection signal from the selection signal terminal to transmit a driving current from the connected driving transistor to the light-emitting device, wherein within a frame period, one of a plurality of selection signal terminals respectively electrically connected to the plurality of gating sub-circuits outputs a selection signal;
a light-emitting control sub-circuit electrically connected to a light-emitting control signal terminal, a first voltage signal terminal, the plurality of driving transistors and the plurality of gating sub-circuits, and the light-emitting control sub-circuit being configured to create a path between each driving transistor and a respective gating sub-circuit under control of a light-emitting control signal from the light-emitting control signal terminal; and
at least one initialization sub-circuit; each initialization sub-circuit being electrically connected to an initialization signal terminal, a second voltage signal terminal, a control electrode of at least one driving transistor and the light-emitting device node, and the initialization sub-circuit being configured to transmit a second voltage signal from the second voltage signal terminal to both a control electrode of the at least one driving transistor and the light-emitting device under control of an initialization signal from the initialization signal terminal.

2. The pixel circuit according to claim 1 , wherein channel regions of the plurality of driving transistors have different width-to-length ratios.

3. The pixel circuit according to claim 1 , wherein each gating sub-circuit is further electrically connected to the second voltage signal terminal; and the gating sub-circuit includes:
a first transistor, a control electrode of the first transistor being electrically connected to the scanning signal terminal, a first electrode of the first transistor being electrically connected to the selection signal terminal, and a second electrode of the first transistor being electrically connected to a first node;
a second transistor, a control electrode of the second transistor being electrically connected to the first node, a first electrode of the second transistor being electrically connected to the driving transistor, and a second electrode of the second transistor being electrically connected to the light-emitting device node; and
a first capacitor, a first electrode plate of the first capacitor being electrically connected to the first node, and a second electrode plate of the first capacitor being electrically connected to the second voltage signal terminal.

4. The pixel circuit according to claim 1 , further comprising:
a data writing sub-circuit electrically connected to the scanning signal terminal, a data signal terminal and control electrodes of the plurality of driving transistors, and the data writing sub-circuit being configured to transmit a data signal from the data signal terminal to the control electrodes of the plurality of driving transistors under control of the scanning signal.

5. The pixel circuit according to claim 4 , wherein the data writing sub-circuit includes:
a third transistor, a control electrode of the third transistor being electrically connected to the scanning signal terminal, a first electrode of the third transistor being electrically connected to the data signal terminal, and a second electrode of the third transistor being electrically connected to the control electrodes of the plurality of driving transistors.

6. The pixel circuit according to claim 1 , further comprising:
a data writing sub-circuit electrically connected to the scanning signal terminal, a data signal terminal and first electrodes of the plurality of driving transistors, and the data writing sub-circuit being configured to transmit a data signal from the data signal terminal to the first electrodes of the plurality of driving transistors under control of the scanning signal; and
at least one compensation sub-circuit, each compensation sub-circuit being electrically connected to the scanning signal terminal, a second electrode of a driving transistor in the plurality of driving transistors and a control electrode of the at least one driving transistor, and the compensation sub-circuit being configured to transmit a voltage signal of the second electrode of the driving transistor to the control electrode of the at least one driving transistor under the control of the scanning signal.

7. The pixel circuit according to claim 6 , wherein the at least one compensation sub-circuit includes a single compensation sub-circuit, and the single compensation sub-circuit is electrically connected to the second electrode of the driving transistor in the plurality of driving transistors and a control electrode of each driving transistor; or
the at least one compensation sub-circuit includes a plurality of compensation sub-circuits, and each compensation sub-circuit is electrically connected to the second electrode of the driving transistor and a control electrode of the driving transistor.

8. The pixel circuit according to claim 6 , wherein
the data writing sub-circuit includes a fourth transistor; a control electrode of the fourth transistor is electrically connected to the scanning signal terminal, a first electrode of the fourth transistor is electrically connected to the data signal terminal, and a second electrode of the fourth transistor is electrically connected to the first electrodes of the plurality of driving transistors; and
each compensation sub-circuit includes a fifth transistor; a control electrode of the fifth transistor is electrically connected to the scanning signal terminal, a first electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the control electrode of the at least one driving transistor.

9. The pixel circuit according to claim 1 , wherein the at least one initialization sub-circuit includes a single initialization sub-circuit, and the single initialization sub-circuit is electrically connected to control electrodes of the plurality of driving transistors; or
the at least one initialization sub-circuit includes a plurality of initialization sub-circuits, and each initialization sub-circuit is electrically connected to a control electrode of a driving transistor.

10. The pixel circuit according to claim 1 , wherein
the light-emitting control sub-circuit includes a sixth transistor and a plurality of seventh transistors; a control electrode of the sixth transistor is electrically connected to the light-emitting control signal terminal, a first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the sixth transistor is electrically connected to first electrodes of the plurality of driving transistors; a control electrode of each seventh transistor is electrically connected to the light-emitting control signal terminal, a first electr

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Fangzhen
• Niu Jing
• Sun Shuang
• Zhang Zhenyu

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title