Open block family duration limited by time and temperature

Patent metadata

Field	Value
Publication number	US-12293099-B2
Application number	US-202318098439-A
Country	US
Kind code	B2
Filing date	Jan 18, 2023
Priority date	Aug 19, 2020
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer at initialization of the block family;
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open;
storing, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is open;
detecting a power on of the system;
measuring a data state metric associated with memory cells of the pages, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution;
estimating a time after program value of the pages based on comparing a level of the data state metric to a temporal voltage shift function;
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value; and
closing the block family based on the incremented value of the timer.

2. The system of claim 1 , wherein the timer is associated with a system clock.

3. The system of claim 1 , wherein the operations further comprise:
aggregating a plurality of temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature;
responsive to programming a first page residing on the memory device, associating the first page with the block family;
determining that the timer has reached a first time value in response to the aggregate temperature being greater than a first temperature value;
wherein closing the block family is in response to the timer reaching the first time value;
determining that the timer has reached a second time value, which is greater than the first time value, in response to the aggregate temperature being less than or equal to the first temperature value; and
wherein closing the block family is in response to the timer reaching the second time value.

4. The system of claim 3 , wherein, for use of the first time value, the aggregate temperature is between the first temperature value and a second temperature value that is higher than the first temperature value, and wherein the operations further comprise:
responsive to closing the block family, initializing a new block family;
responsive to programming a second page residing on the memory device, associating the second page with the new block family;
closing the new block family in response to the aggregate temperature being between the first temperature value and the second temperature value and the timer reaching the first time value; and
closing the new block family in response to the aggregate temperature being greater than or equal to the second temperature value and the timer reaching a third time value that is less than the first time value.

5. The system of claim 1 , wherein the operations further comprise, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.

6. The system of claim 1 , wherein the operations further comprise:
tracking, using a circuit-level clock, a second time period the memory device is powered off;
detecting the power on of the system; and
updating the value of the timer, restored from the non-volatile memory, based on the second time period.

7. A method comprising:
initializing, by a processing device, a block family associated with a memory device;
initializing a timer at initialization of the block family;
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open;
storing, in non-volatile memory of the memory device, a value of the timer before powering down the memory device while the block family is open;
detecting a power on of the memory device;
measuring a data state metric associated with memory cells of the pages, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution;
estimating a time after program value of the pages based on comparing a level of the data state metric to a temporal voltage shift function;
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value; and
closing the block family based on the value of the timer.

8. The method of claim 7 , wherein the timer is associated with a system clock.

9. The method of claim 7 , further comprising:
aggregating a plurality of temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature;
responsive to programming a first page residing on the memory device, associating the first page with the block family;
determining that the timer has reached a first time value in response to the aggregate temperature being greater than a first temperature value;
wherein closing the block family is in response to the timer reaching the first time value;
determining that the timer has reached a second time value, which is greater than the first time value, in response to the aggregate temperature being less than or equal to the first temperature value; and
wherein closing the block family is in response to the timer reaching the second time value.

10. The method of claim 9 , wherein, for use of the first time value, the aggregate temperature is between the first temperature value and a second temperature value that is higher than the first temperature value, the method further comprising:
responsive to closing the block family, initializing a new block family;
responsive to programming a second page residing on the memory device, associating the second page with the new block family;
closing the new block family in response to the aggregate temperature being between the first temperature value and the second temperature value and the timer reaching the first time value; and
closing the new block family in response to the aggregate temperature being greater than or equal to the second temperature value and the timer reaching a third time value that is less than the first time value.

11. The method of claim 7 , further comprising, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.

12. A memory sub-system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer at initialization of the block family;
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open;
storing, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is open;
detecting a power on of the system;
measuring a data state metric associated with memory cells of the pages, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution;
estimating a time after program value of the pages based on comparing a level of the data state metric to a temporal voltage shift function;
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value; and
closing the block family based on the value of the timer.

13. The memory sub-system of claim 12 , wherein the timer is associated with a system c

Assignees

• Micron Technology Inc

Inventors

• Sheperek Michael
• Koudele Larry J
• Liikanen Bruce A
• Kientz Steven Michael
• Muchherla Kishore Kumar

Classifications

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G01K3/04

  in respect of time · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title