Shared well structure manufacturing method

Patent metadata

Field	Value
Publication number	US-12288786-B2
Application number	US-202318518706-A
Country	US
Kind code	B2
Filing date	Nov 24, 2023
Priority date	Jun 9, 2021
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit (IC) structure, the method comprising:
configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction; and
forming IC devices comprising a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well,
wherein the forming the IC devices comprises forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.

2. The method of claim 1 , wherein the configuring each of the n-well and the p-well to have the second and third portions extending from the first portion in the second direction comprises the second and third portions of the n-well and p-well having an interdigitated configuration.

3. The method of claim 1 , wherein
the configuring the n-well comprises performing an implantation process on a p-type substrate, and
the configuring the p-well comprises configuring an area outside the n-well as the p-well based on being a portion of the p-type substrate.

4. The method of claim 1 , wherein the forming the IC devices comprises:
forming a first electrical connection from the first pickup structure to a first power distribution structure configured to have a power supply voltage; and
forming a second electrical connection from the second pickup structure to a second power distribution structure configured to have a reference voltage.

5. The method of claim 1 , further comprising constructing a through-silicon-via (TSV) structure in the first IC die adjacent to the first portion of the n-well or the first portion of the p-well.

6. The method of claim 5 , further comprising electrically connecting the TS V structure to a second IC die of an IC package.

7. The method of claim 1 , wherein the forming the IC devices further comprises forming a device block in the first IC die adjacent to the first portion of the n-well or the first portion of the p-well.

8. The method of claim 1 , wherein
the n-well is a first n-well of a plurality of n-wells,
the p-well is a first p-well of a plurality of p-wells, and
the configuring each of the n-well and the p-well in the first IC die comprises configuring each n-well of the plurality of n-wells and each p-well of the plurality of p-wells to have the first portion extending in the first direction and second and third portions extending from the first portion in the second direction.

9. A method of manufacturing an integrated circuit (IC) structure, the method comprising:
configuring each of a first n-well and a first p-well in an IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction;
forming IC devices comprising a first pickup structure electrically connected to the first n-well and a second pickup structure electrically connected to the first p-well; and
constructing a first through-silicon-via (TSV) structure in the IC die adjacent to one of the first portion of the first n-well or the first portion of the first p-well.

10. The method of claim 9 , wherein the constructing the first TSV structure comprises:
constructing a TSV spanning front and back sides of the IC die and surrounded by a TSV isolation structure,
wherein the TSV isolation structure is positioned between the TSV and the one of the first portion of the first n-well or the first portion of the first p-well.

11. The method of claim 9 , wherein the constructing the first TSV structure comprises:
constructing a second TSV structure in the IC die adjacent to the other of the first portion of the first n-well or the first portion of the first p-well.

12. The method of claim 11 , wherein
the configuring each of the first n-well and the first p-well comprises configuring each of a second n-well and a second p-well in the IC die to have a first portion extending in the first direction and second and third portions extending from the first portion in the second direction, and
the forming the IC devices comprises the IC devices further comprising a third pickup structure electrically connected to the second n-well and a fourth pickup structure electrically connected to the second p-well.

13. The method of claim 12 , wherein
the constructing the second TSV structure further comprises constructing the second TSV structure in the IC die adjacent to one of the first portion of the second n-well or the first portion of the second p-well, and
the constructing the first TSV structure further comprises constructing a third TSV structure in the IC die adjacent to the other of the first portion of the second n-well or the first portion of the second p-well.

14. The method of claim 12 , wherein the constructing the first TSV structure further comprises:
constructing the first TSV structure in the IC die adjacent to one of the first portion of the second n-well or the first portion of the second p-well, and
constructing the second TSV structure in the IC die adjacent to the other of the first portion of the second n-well or the first portion of the second p-well.

15. A method of manufacturing an integrated circuit (IC) structure, the method comprising:
configuring each of an n-well and a p-well in an IC die to have a first portion extending in a first direction and second through fourth portions extending from the first portion in a second direction perpendicular to the first direction, wherein the third portion is positioned between the second and fourth portions; and
forming IC devices comprising a first pickup structure positioned in and electrically connected to the second portion of the n-well, a second pickup structure positioned in and electrically connected to the second portion of the p-well, a third pickup structure positioned in and electrically connected to the fourth portion of the n-well, and a fourth pickup structure positioned in and electrically connected to the fourth portion of the p-well.

16. The method of claim 15 , wherein the forming the IC devices comprises the first and third portions of each of the n-well and p-well being free from including a pickup structure.

17. The method of claim 15 , wherein the forming the IC devices comprising the first though fourth pickup structures comprises aligning the first though fourth pickup structures in the first direction.

18. The method of claim 15 , wherein the forming the IC devices further comprises:
forming a first row of IC devices comprising a first part of the third portion of one of the n-well or the p-well; and
forming a second row of IC devices comprising a second part of the third portion of the one of the n-well or the p-well.

19. The method of claim 18 , wherein
the forming the first through fourth pickup structures comprises forming a plurality of pickup structures comprising a total number of pickup structures,
the forming the first and second rows of IC devices comprises forming a plurality of rows of IC devices comprising parts of corresponding portions of the one of the n-well or the p-well,
the plurality of rows of IC devices comprises a total number of rows of IC devices, and
a ratio of the total number of rows of IC devices to the total number of pickup structures has a value ranging from ten to thirty.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc China Company Ltd
• Tsmc Nanjing Company Ltd

Inventors

• Zhou Yang
• Han Liu
• Meng Qingchao
• Wang Xinyong
• Cai Zejian

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title