Semiconductor package

Patent metadata

Field	Value
Publication number	US-12288780-B2
Application number	US-202217824194-A
Country	US
Kind code	B2
Filing date	May 25, 2022
Priority date	Sep 3, 2021
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

A semiconductor package including: a package substrate; an interposer on the package substrate; a chip stack on the interposer, the chip stack including a plurality of first semiconductor chips that are stacked in a first direction; a second semiconductor chip on the interposer and spaced apart from the chip stack in a second direction intersecting the first direction; and a first signal pad, a second signal pad, and a power/ground pad on a top surface of the interposer, wherein the chip stack is mounted on the first signal pad, wherein the second semiconductor chip is mounted on the second signal pad, wherein the chip stack and the second semiconductor chip are connected to the power/ground pad, and wherein the power/ground pad overlaps a portion of the chip stack and a portion of the second semiconductor chip.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate;
an interposer on the package substrate;
a chip stack on the interposer, the chip stack including a plurality of first semiconductor chips that are stacked in a first direction;
a second semiconductor chip on the interposer and spaced apart from the chip stack in a second direction intersecting the first direction; and
a first signal pad, a second signal pad, and a power/ground pad on a top surface of the interposer,
wherein the chip stack is mounted on the first signal pad,
wherein the second semiconductor chip is mounted on the second signal pad,
wherein the chip stack and the second semiconductor chip are connected to the power/ground pad, and
wherein the power/ground pad overlaps a portion of the chip stack and a portion of the second semiconductor chip.

2. The semiconductor package of claim 1 , wherein a top surface of the power/ground pad at a same level a top surface of the first signal pad and a top surface of the second signal pad.

3. The semiconductor package of claim 1 , wherein the power/ground pad, the first signal pad, and the second signal pad protrude from the top surface of the interposer.

4. The semiconductor package of claim 1 , wherein the interposer includes:
a first wiring layer that has a first dielectric pattern and a power/ground pattern in the first dielectric pattern; and
a second wiring layer on the first wiring layer, the second wiring layer having a second dielectric pattern and a signal pattern in the second dielectric pattern,
wherein the power/ground pad vertically overlaps the signal pattern.

5. The semiconductor package of claim 4 , wherein the signal pattern is between the power/ground pattern and the power/ground pad.

6. The semiconductor package of claim 4 , wherein the power/ground pad, the first signal pad, and the second signal pad are on a top surface of the second dielectric pattern.

7. The semiconductor package of claim 4 , wherein
each of the first wiring layer and the second wiring layer is provided in plural,
the plurality of first wiring layers are stacked alternately with the plurality of second wiring layers,
one of the plurality of second wiring layers is a topmost wiring layer of the interposer, and
the power/ground patterns of the plurality of first wiring layers overlap the signal patterns of the plurality of second wiring layers.

8. The semiconductor package of claim 1 , wherein, when viewed in a plan view, the power/ground pad covers a region between the chip stack and the second semiconductor chip.

9. The semiconductor package of claim 1 , wherein the chip stack further includes a plurality of dummy bumps that are on bottom surfaces of the plurality of first semiconductor chips and are electrically insulated from the plurality of first semiconductor chips,
wherein the dummy bump on the bottom surface of a lowermost one of the plurality of first semiconductor chips is connected to the power/ground pad.

10. The semiconductor package of claim 9 , wherein
the dummy bumps are adjacent to a lateral surface of the chip stack, the lateral surface adjacent to the second semiconductor chip, and
the dummy bumps are connected to each other through a plurality of dummy through electrodes that penetrate the plurality of first semiconductor chips.

11. The semiconductor package of claim 1 , further comprising a shielding member connected to a top surface of the power/ground pad,
wherein the shielding member extends from the top surface of the power/ground pad and is disposed between the chip stack and the second semiconductor chip.

12. The semiconductor package of claim 1 , wherein
the chip stack is connected to the first signal pad through a first solder ball and to the power/ground pad through a second solder ball, and
the second semiconductor chip is connected to the second signal pad through a third solder ball and to the power/ground pad through a fourth solder ball.

13. The semiconductor package of claim 1 , wherein
the chip stack is provided in plural, the plurality of chip stacks being spaced apart from each other on the interposer,
the second semiconductor chip is between the plurality of chip stacks,
the power/ground pad is provided in plural, each of the plurality of power/ground pads being between the second semiconductor chip and one of the chip stacks,
each of the plurality of chip stacks is connected to one of the plurality of power/ground pads, and
the second semiconductor chip is connected to each of the plurality of power/ground pads.

14. The semiconductor package of claim 1 , wherein
the first semiconductor chips include a memory chip, and
the second semiconductor chip includes a logic chip.

15. A semiconductor package, comprising:
a package substrate;
an interposer on the package substrate;
a chip stack on the interposer, the chip stack including a plurality of first semiconductor chips that are stacked on each other; and
a second semiconductor chip on the interposer and spaced apart from the chip stack,
wherein the interposer includes:
a first wiring layer that has a power/ground pattern;
a second wiring layer on the first wiring layer, the second wiring layer having a signal pattern; and
a first signal pad and a first power/ground pad disposed on the second wiring layer and on which the chip stack is mounted;
a second signal pad and a second power/ground pad disposed on the second wiring layer and on which the second semiconductor chip is mounted; and
a connection pattern that electrically connects the first power/ground pad to the second power/ground pad,

wherein the connection pattern vertically overlaps the signal pattern of the second wiring laver.

16. The semiconductor package of claim 15 , wherein
the first power/ground pad, the second power/ground pad, and the connection pattern constitute a power/ground pad that is provided in a single unitary piece, and
when viewed in a plan view, the power/ground pad covers a region between the chip stack and the second semiconductor chip.

17. The semiconductor package of claim 16 , wherein the power/ground pad overlaps a portion of the chip stack and a portion of the second semiconductor chip.

18. The semiconductor package of claim 15 , wherein the connection pattern bas a linear shape that connects the first power/ground pad to the second power/ground pad.

19. The semiconductor package of claim 15 , wherein the first signal pad, the first power/ground pad, the second signal pad and the second power/ground pad protrude from a top surface of the second wiring layer.

20. The semiconductor package of claim 15 , wherein the signal pattern of the second wiring layer is between the power/ground pattern of the first wiring layer and the connection pattern.

21. The semiconductor package of claim 15 , wherein the first signal pad, the first power/ground pad, the second signal pad, the second power/ground pad, and the connection pattern have top surfaces at the same level.

22. The semiconductor package of claim 15 , wherein the plurality of first semiconductor chips include a plurality of dummy through electrodes that penetrate the plurality of first semiconductor chips and are electrically insulated from integrated circuits of the plurality of first semiconductor chips,
wherein the dummy through electrodes are connected to the second power/ground pad.

23. The semiconductor package of claim 15 , further compris

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Ju-Youn
• Suk Kyoung Lim
• Lee Wonjae

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title