Embedded memory device and method for embedding memory device in a substrate

Patent metadata

Field	Value
Publication number	US-11018124-B2
Application number	US-201816119837-A
Country	US
Kind code	B2
Filing date	Aug 31, 2018
Priority date	Aug 31, 2018
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

First claim

The invention claimed is:

1. An electronic package comprising:
a substrate comprising a cavity;
a memory device embedded in the cavity and comprising input/output (I/O) memory device pads, the memory device comprising a redistribution layer, wherein a portion of the substrate is over the redistribution layer;
a processor disposed on the substrate and comprising I/O processor pads, the I/O processor and memory device pads vertically aligned and electrically connected; and
another memory device disposed over a surface of the substrate, the another memory device partially overlapping the memory device, wherein the another memory device is communicatively coupled to the processor by the redistribution layer of the memory device.

2. The package of claim 1 , wherein the memory device comprises a plurality of contact pads that include the I/O memory device pads, ground pads connected with ground, power pads connected with power and test pads to test and debug the memory device, the test pads disposed on an opposite edge of the memory device as the I/O memory device pads.

3. The package of claim 1 , wherein the memory device and the processor partially overlap such that the memory device and the processor extend laterally in opposite directions from the I/O processor and memory device pads.

4. The package of claim 1 , further comprising power and ground strips disposed on a surface of the substrate extending a direction perpendicular to a direction of extension of the memory device from the processor, the power and ground strips having a length longer than a width of the memory device.

5. The package of claim 1 , further comprising a ground plane and attach film, the attach film disposed between the ground plane and the memory device to attach the memory device to the ground plane.

6. The package of claim 1 , further comprising a redistribution layer formed within the substrate between the memory device and a surface of the substrate, the redistribution layer electrically coupling I/O contact pads of the other memory device and other I/O processor contact pads of the processor.

7. The package of claim 6 , wherein:
the redistribution layer is formed on a portion of a first conductive layer, and
at least one of power or ground signals are formed on another portion of the first conductive layer and on a second conductive layer between the memory device and the redistribution layer.

8. The package of claim 1 , further comprising an organic layer formed within the substrate between the memory device and the other memory device, the organic layer comprising signal lines having spacing.

9. The package of claim 1 , wherein the other memory device is disposed on the surface of the substrate laterally adjacent to the processor and extends from the memory device in an opposite direction from a direction of extension of the processor from the memory device.

10. The package of claim 1 , wherein the another memory device is disposed on and partially overlaps the processor, and I/O contact pads of the other memory device and other I/O processor contact pads of the processor are vertically aligned and connected through one or more Through Silicon Vias (TSVs).

11. The package of claim 10 , further comprising a spacer disposed adjacent to the processor and between the another memory device and the substrate to support a portion of the other memory device that overhangs from the processor.

12. The package of claim 9 , further comprising a heat dissipater disposed on the processor and adjacent to the other memory device.

13. An electronic package comprising:
a substrate comprising a cavity;
a memory device embedded in the cavity, the memory device comprising a redistribution layer, wherein a portion of the substrate is over the redistribution layer;
a processor disposed over a surface of the substrate skewed to partially overlap the memory device;
input/output (I/O) interconnects that connect the processor and memory device for data storage and retrieval in the memory device, the I/O interconnects having a pitch substantially less than a pitch of ground and power interconnects to the memory device; and
another memory device disposed over the surface of the substrate, the another memory device partially overlapping the memory device on an opposite side of the memory device as the processor, wherein the another memory device is communicatively coupled to the processor by the redistribution layer of the memory device.

Assignees

• Intel Corp

Inventors

• Collins Andrew

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W90/722

  between stacked chips · CPC title