Conformal power delivery structure for direct chip attach architectures

US12288750B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12288750-B2
Application numberUS-202117485208-A
CountryUS
Kind codeB2
Filing dateSep 24, 2021
Priority dateSep 24, 2021
Publication dateApr 29, 2025
Grant dateApr 29, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

First claim

Opening claim text (preview).

The invention claimed is: 1. An apparatus comprising: first connection pads on a first surface of the apparatus; second connection pads on a second surface of the apparatus opposite the first surface; a conformal power delivery structure comprising: a first electrically conductive layer comprising metal, the first electrically conductive layer defining one or more recesses; a second electrically conductive layer comprising metal, the second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with an upper surface of the first electrically conductive layer; and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another; wherein the first electrically conductive layer is connected to a first set of the first connection pads, and the second electrically conductive layer is connected to a second set of the first connection pads and to a set of the second connection pads; and bridge circuitry to connect a first integrated circuit (IC) chip with a second IC chip, the bridge circuitry connected to a third set of first connection pads different from the first set and the second set of first connection pads. 2. The apparatus of claim 1 , wherein the first electrically conductive layer comprises a first portion and a second portion electrically isolated from one another, the first portion connected to the first set of the first connection pads and the second portion connected to a second set of the second connection pads. 3. The apparatus of claim 1 , wherein conformal power delivery structure is a first conformal power delivery structure, and the apparatus further comprises a second conformal power delivery structure comprising: a third electrically conductive layer comprising metal, the third electrically conductive layer defining one or more recesses; a fourth electrically conductive layer comprising metal, the fourth electrically conductive layer at least partially within the recesses of the third electrically conductive layer and having a lower surface that generally conforms with an upper surface of the third electrically conductive layer; and a dielectric material between the surfaces of the third electrically conductive layer and the fourth electrically conductive layer that conform with one another; wherein the third electrically conductive layer is connected to a second set of the second connection pads and the fourth electrically conductive layer is connected to a fourth set of the second connection pads. 4. The apparatus of claim 1 , wherein: the second electrically conductive layer defines one or more recesses; and the conformal power delivery structure comprises: a third electrically conductive layer comprising metal, the third electrically conductive layer at least partially within the recesses of the second electrically conductive layer and having a lower surface that generally conforms with an upper surface of the second electrically conductive layer; a dielectric material between the surfaces of the second electrically conductive layer and the third electrically conductive layer that conform with one another; and the third electrically conductive layer is connected to a second set of the second connection pads. 5. The apparatus of claim 1 , further comprising a redistribution layer connected to at least one of the first connection pads. 6. The apparatus of claim 1 , further comprising a redistribution layer connected to at least one of the second connection pads. 7. The apparatus of claim 1 , further comprising a set of pillars between respective pairs of the first connection pads and the second connection pads, the pillars comprising metal. 8. The apparatus of claim 1 , wherein the first connection pads have a pitch between approximately 10-150 um, and the second connection pads have a pitch between approximately 150-250 um. 9. A chip package comprising: a first integrated circuit (IC) chip; a second IC chip; base die apparatus connected to the first and second IC chips through first connection pads on a first surface of the base die apparatus, the base die apparatus comprising: bridge circuitry connected to each of the first and second IC chips; a conformal power delivery structure comprising: a first electrically conductive layer comprising metal, the first electrically conductive layer defining one or more recesses; a second electrically conductive layer comprising metal, the second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with an upper surface of the first electrically conductive layer; and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another; wherein the first electrically conductive layer and second electrically conductive layer of the conformal power delivery structure are each connected to one or both of the first IC chip and the second IC chip; and second connection pads on a second surface of the base die apparatus opposite the first surface. 10. The chip package of claim 9 , wherein: the first IC chip comprises voltage regulator circuitry; and the first electrically conductive layer comprises a first portion and a second portion electrically isolated from one another, the first portion connected to an output voltage terminal of the voltage regulator circuitry and to processor circuitry of one or both of the first IC chip and the second IC chip, the second portion connected to a set of the second connection pads and to an input voltage terminal of the voltage regulator circuitry. 11. The chip package of claim 9 , wherein: the first IC chip comprises voltage regulator circuitry; and the conformal power delivery structure is a first conformal power delivery structure, and the apparatus further comprises a second conformal power delivery structure comprising: a third electrically conductive layer comprising metal, the third electrically conductive layer defining one or more recesses; a fourth electrically conductive layer comprising metal, the fourth electrically conductive layer at least partially within the recesses of the third electrically conductive layer and having a lower surface that generally conforms with an upper surface of the third electrically conductive layer; and a dielectric material between the surfaces of the third electrically conductive layer and the fourth electrically conductive layer that conform with one another; wherein the third electrically conductive layer is connected to a set of the second connection pads and to an input voltage terminal of the voltage regulator circuitry, and the first electrically conductive layer is connected to an output voltage terminal of the voltage regulator circuitry and to processor circuitry of one or both of the first IC chip and the second IC chip. 12. The chip package of claim 9 , wherein: the first IC chip comprises voltage regulator circuitry; and the second electrically conductive layer defines one or more recesses; and the conformal power delivery structure comprises: a third electrically conductive layer comprising metal, the third electrically conductive layer at least partially within the recesses of the second electrically conductive layer and having a lower surface that generally conforms with an upper surface of the second electrically conductive layer; a dielectric material between the surfaces of th

Assignees

Inventors

Classifications

  • the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

  • Vias, e.g. via plugs · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Package configurations · CPC title

  • comprising multiple insulating layers · CPC title

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What does patent US12288750B2 cover?
In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conduc…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/611. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 29 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).