Array substrate, display panel and manufacturing method thereof

US12288726B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12288726-B2
Application numberUS-202117764256-A
CountryUS
Kind codeB2
Filing dateMay 27, 2021
Priority dateMay 28, 2020
Publication dateApr 29, 2025
Grant dateApr 29, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An array substrate, a display panel and methods of manufacturing the same are provided. The method of manufacturing an array substrate according to an embodiment of the present disclosure includes: forming f pixel electrodes and a conductive structure on a substrate through a patterning process, wherein the pixel electrodes arranged in a first direction are connected through the conductive structure; and forming a signal line on the substrate through a patterning process, wherein the signal line and the pixel electrodes are disposed in the same layer. By means of the array substrate according to the embodiments of the present disclosure, the problem that it is not easy to discover the point defects caused by short circuit between the signal line and pixel electrodes in the related art can be solved.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing an array substrate, comprising: forming pixel electrodes and a conductive structure on a substrate through a patterning process, wherein the pixel electrodes arranged in a first direction are connected through the conductive structure; and forming a signal line on the substrate through a patterning process, wherein the signal line and the pixel electrodes are disposed in the same layer; forming an insulating layer on the substrate formed with the signal line; performing a short circuit detection of the signal line on the array substrate; removing the conductive structure through an etching process, so as to insulate and disconnect different pixel electrodes; and after removing the conductive structure, filling an insulating material at a position corresponding to the conductive structure so as to insulate between the adjacent pixel electrodes, wherein a surface of the insulating material opposite to the substrate is positioned at a level between a surface of the insulating layer opposite to the substrate and a surface of each of the pixel electrodes opposite to the substrate. 2. The method of claim 1 , wherein the conductive structure and the pixel electrodes are disposed in the same layer and made of a same material. 3. The method of claim 1 , wherein the first direction is the same as an extending direction of the signal line. 4. The method of claim 1 , wherein the pixel electrodes are arranged in an array; the pixel electrodes in the same row are connected through the conductive structure; and the signal line extends in a row direction of the array. 5. The method of claim 1 , wherein after performing the short circuit detection on the array substrate, the method further comprises: etching the insulating layer to expose the conductive structure; forming a common electrode layer on the substrate; and etching the substrate formed with the common electrode layer to form a common electrode at the same time of removing the conductive structure. 6. A method of manufacturing a display panel, comprising: manufacturing an array substrate by the method of manufacturing an array substrate according to claim 1 . 7. The method of claim 6 , wherein the conductive structure and the pixel electrodes are disposed in the same layer and made of a same material. 8. The method of claim 6 , wherein the first direction is the same as an extending direction of the signal line. 9. The method of claim 6 , wherein the pixel electrodes are arranged in an array; the pixel electrodes in the same row are connected through the conductive structure; and the signal line extends in a row direction of the array. 10. The method of claim 6 , wherein after performing the short circuit detection on the array substrate, the method further comprises: etching the insulating layer to expose the conductive structure; forming a common electrode layer on the substrate; and etching the substrate formed with the common electrode layer to form a common electrode at the same time of removing the conductive structure. 11. A display panel, comprising the array substrate manufactured by the method of manufacturing an array substrate according to claim 1 . 12. An array substrate, comprising: a substrate, pixel electrodes and a signal line disposed on the substrate, wherein the pixel electrodes and the signal line are disposed in the same layer; an insulating layer is formed on the substrate formed with the pixel electrodes and the signal line; a through-hole is disposed between the adjacent pixel electrodes arranged in a first direction in a layer of the pixel electrodes; and the through-hole spaces between the adjacent pixel electrodes, and the through-hole is filled with an insulating material, wherein a surface of the insulating material opposite to the substrate is positioned at a level between a surface of the insulating layer opposite to the substrate and a surface of each of the pixel electrodes opposite to the substrate.

Assignees

Inventors

Classifications

  • characterised by multiple measurements, corrections, marking or sorting processes · CPC title

  • H10P74/27Primary

    Structural arrangements therefor · CPC title

  • adapted for preventing breakage, peeling or short circuiting · CPC title

  • Interconnections, e.g. scanning lines · CPC title

  • wherein the TFTs are in active matrices · CPC title

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What does patent US12288726B2 cover?
An array substrate, a display panel and methods of manufacturing the same are provided. The method of manufacturing an array substrate according to an embodiment of the present disclosure includes: forming f pixel electrodes and a conductive structure on a substrate through a patterning process, wherein the pixel electrodes arranged in a first direction are connected through the conductive stru…
Who is the assignee on this patent?
Hefei Xinsheng Optoelectronics Technology Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P74/27. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 29 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).