Array substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-2016276377-A1
Application number	US-201314407707-A
Country	US
Kind code	A1
Filing date	Dec 5, 2013
Priority date	Sep 27, 2013
Publication date	Sep 22, 2016
Grant date	—

Abstract

A method for manufacturing an array substrate, comprising forming a pattern of a gate electrode by one pattering process; forming a gate insulating layer on a substrate provided with the pattern of the gate electrode; forming first and second patterns thereon, in which the first pattern corresponds to a pattern of a semiconductor active layer and the second pattern corresponds to a source electrode and a drain electrode; forming a pattern layer including an opening area on the substrate provided with the second pattern, in which the opening area corresponds to a gap between the source electrode and the drain electrode, the minimum width thereof being greater than the width of the gap between the source electrode and the drain electrode, and at least forming a pattern of the source electrode and the drain electrode and a pixel electrode electrically connected with the drain electrode through the opening area.

First claim

1 . An array substrate, comprising a thin-film transistor (TFT), a pixel electrode and a pattern layer disposed between a source electrode and a drain electrode of the TFT and the pixel electrode, wherein
the pattern layer includes an opening area corresponding to a gap between the source electrode and the drain electrode; the minimum width of the opening area is greater than a width of the gap between the source electrode and the drain electrode and at least a portion of the drain electrode of the TFT is exposed by the opening area; and the pixel electrode is electrically connected with the drain electrode exposed by the opening area.

2 . The array substrate according to claim 1 , wherein the pattern layer includes a transparent organic insulating layer and an adhesion layer disposed beneath the transparent organic insulating layer.

3 . The array substrate according to claim 2 , further comprising a passivation layer and a common electrode disposed on the pixel electrode in sequence,
wherein both the adhesion layer and the transparent organic insulating layer include the opening area.

4 . The array substrate according to claim 2 , further comprising a common electrode and a passivation layer disposed between the transparent organic insulating layer and the pixel electrode in sequence,
wherein the adhesion layer, the transparent organic insulating layer and the passivation layer all include the opening area.

5 . The array substrate according to claim 2 , further comprising a common electrode arranged on a same layer as and alternately with pixel electrode,
wherein both the adhesion layer and the transparent organic insulating layer include the opening area.

6 . The array substrate according to claim 1 , further comprising a transparent electrode retained pattern arranged on the same layer as the pixel electrode,
wherein the transparent electrode retained pattern at least corresponds to the source electrode and is disposed on the source electrode; the source electrode of the TFT is also exposed by the opening area; and the transparent electrode retained pattern is electrically connected with the source electrode exposed by the opening area.

7 . The array substrate according to claim 1 , further comprising a data line, wherein the data line is electrically connected with the transparent electrode retained pattern and/or the source electrode.

8 . The array substrate according to claim 1 , wherein the TFT includes a semiconductor active layer,
wherein the semiconductor active layer includes an amorphous silicon layer and an n+ amorphous silicon layer; or the semiconductor active layer includes a metal oxide semiconductor active layer.

9 . The array substrate according to claim 1 , wherein the TFT is a bottom-gate TFT.

10 . A display device, comprising the array substrate according to claim 1 .

11 . A method for manufacturing an array substrate, comprising:
forming a pattern of a gate electrode on a base substrate by one patterning process; forming a gate insulating layer on the substrate provided with the pattern of the gate electrode; forming a first pattern and a second pattern disposed on the first pattern by one patterning process on the substrate provided with the gate insulating layer, wherein the first pattern corresponds to a pattern of a semiconductor active layer and the second pattern corresponds to a source electrode and a drain electrode to be formed; forming a pattern layer including an opening area on the substrate provided with the second pattern, wherein the opening area corresponds to a gap between the source electrode and the drain electrode to be formed, the minimum width of the opening area is greater than a width of the gap between the source electrode and the drain electrode, and a portion of the drain electrode is exposed by the opening area; and at least forming a pattern of the source electrode and the drain electrode and a pixel electrode on the substrate provided with the pattern layer by one patterning process, wherein the pixel electrode is electrically connected with the drain electrode exposed by the opening area.

12 . The method according to claim 11 , wherein the pattern layer includes an adhesion layer and a transparent organic insulating layer.

13 . The method according to claim 12 , before the process of at least forming the pattern of the source electrode and the drain electrode and the pixel electrode, further comprising:
forming a common electrode by one patterning process; and forming a passivation layer film on the substrate provided with the common electrode, wherein the adhesion layer, the transparent organic insulating layer and a passivation layer, including the opening area, are formed on the substrate provided with the second pattern.

14 . The method according to claim 13 , wherein
before the common electrode and the passivation layer film are formed, an adhesion layer film and a transparent organic insulating layer film are formed on the substrate provided with the second pattern in sequence, the transparent organic insulating layer film is subjected to one patterning process, and the transparent organic insulating layer includes the opening area being formed; and after the common electrode and the passivation layer film are formed, the adhesion layer and the passivation layer, including the opening area, are formed by performing one patterning process on the adhesion layer film and the passivation layer film.

15 . The method according to claim 11 , wherein a common electrode arranged on a same layer as and alternately with pixel electrode is also formed at the same time when the pixel electrode is formed.

16 . The method according to claim 11 , wherein the passivation layer is formed on the substrate provided with the pixel electrode; and subsequently, a common electrode is formed on the passivation layer.

17 . The method according to claim 11 , wherein a transparent electrode retained pattern is also formed at the same time when the pattern of the source electrode and the drain electrode and the pixel electrode are at least formed by one patterning process,
the transparent electrode retained pattern at least corresponds to the source electrode, is disposed on the source electrode, and is electrically connected with a portion of the source electrode exposed by the opening area.

18 . The method according to claim 17 , further comprising a through hole for connecting the data line and the transparent electrode retained pattern,
wherein the transparent electrode retained pattern corresponds to both the source electrode and the data line and is electrically connected with the data line via the through hole formed on the data line.

19 . The method according to claim 12 , wherein a common electrode arranged on a same layer as and alternately with pixel electrode is also formed at the same time when the pixel electrode is formed.

20 . The method according to claim 12 , wherein the passivation layer is formed on the substrate provided with the pixel electrode; and subsequently, a common electrode is formed on the passivation.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Sun Shuang

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title