Display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12288527-B2
Application number	US-202418421549-A
Country	US
Kind code	B2
Filing date	Jan 24, 2024
Priority date	Dec 23, 2020
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

A display panel includes: a substrate, sub-pixels and a gate drive circuit. The sub-pixel includes a pixel drive circuit. The gate drive circuit includes cascaded shift registers, and a shift register is electrically connected to pixel drive circuits in a row of sub-pixels. The gate drive circuit further includes cascade input signal lines and cascade display reset signal lines. The cascade input signal line is configured to connect a shift signal terminal and an input signal terminal of two different shift register; and the cascade display reset signal line is configured to connect a shift signal terminal and a display reset signal terminal of two different shift register. The display panel has sub-pixel regions for arranging the sub-pixels and first gap regions each located between two adjacent columns of sub-pixel regions; the cascade display reset signal lines and the cascade input signal lines are disposed in different first gap regions.

First claim

What is claimed is:

1. A display panel, comprising:
a substrate;
a plurality of sub-pixels disposed on a side of the substrate; the plurality of sub-pixels being arranged in a plurality of rows and a plurality of columns, sub-pixels in a row being arranged in a first direction and sub-pixels in a column being arranged in a second direction; and a sub-pixel including a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit; and
a gate drive circuit located on a same side of the substrate as the plurality of sub-pixels, wherein the gate drive circuit includes a plurality of cascaded shift registers, and a shift register is electrically connected to a plurality of pixel drive circuits in a row of sub-pixels; the shift register includes a plurality of device groups, and a device group is located in a region between two adjacent sub-pixels in the corresponding row of sub-pixels; and the device group includes at least one transistor and/or at least one capacitor; wherein
the gate drive circuit further includes a plurality of cascade input signal lines and a plurality of cascade display reset signal lines; a cascade input signal line is configured to connect a shift signal terminal of one shift register and an input signal terminal of another shift register; and a cascade display reset signal line is configured to connect a shift signal terminal of one shift register and a display reset signal terminal of another shift register; and
the display panel has a plurality of sub-pixel regions for arranging the plurality of sub-pixels and first gap regions each located between two adjacent columns of sub-pixel regions; and the cascade display reset signal lines and the cascade input signal lines are disposed in the first gap regions, and both are disposed in different first gap regions; wherein
among device groups included in different shift registers, device groups with a same structure are located in a same region between two adjacent columns of sub-pixels; and/or
no device group is arranged in first gap regions where the cascade display reset signal lines or the cascade input signal lines are disposed; and/or
in the second direction, any three adjacent rows of sub-pixel regions are a first row of sub-pixel regions, a second row of sub-pixel regions, and a third row of sub-pixel regions, the pixel drive circuit includes a first sensing signal line located in a third gap region and extending along the first direction; and the plurality of sub-pixels are divided into a plurality of pixel units, and a pixel unit includes at least three sub-pixels arranged in sequence in the first direction; and in sub-pixels located in the second row of sub-pixel regions and the third row of sub-pixel regions, two pixel units opposite to each other in the second direction share the first sensing signal line.

2. The display panel according to claim 1 , wherein the plurality of cascade input signal lines are divided into a plurality of groups, each group of cascade input signal lines includes at least one cascade input signal line, and at least one group of cascade input signal lines is disposed in a first gap region; and
the plurality of cascade display reset signal lines are divided into a plurality of groups, each group of cascade display reset signal lines includes at least one cascade display reset signal line, and at least one group of cascade display reset signal lines is disposed in a first gap region.

3. The display panel according to claim 2 , wherein at least one column of sub-pixels is disposed between two adjacent groups of cascade input signal lines located in different first gap regions; and at least one column of sub-pixels is disposed between two adjacent groups of cascade display reset signal lines located in different first gap regions; or
wherein groups of cascade input signal lines are disposed in the first gap region, and at least one row of sub-pixels is disposed between two adjacent groups of cascade input signal lines located in a same first gap region; and groups of cascade display reset signal lines are disposed in the first gap region, and at least one row of sub-pixels is disposed between two adjacent groups of cascade display reset signal lines located in a same first gap region.

4. The display panel according to claim 1 , further comprising:
a plurality of data lines extending along the second direction; a data line being electrically connected to pixel drive circuits in a column of sub-pixels; wherein the plurality of cascade input signal lines, the plurality of cascade display reset signal lines, and the plurality of data lines are made of a same material and disposed in a same layer.

5. The display panel according to claim 1 , wherein the plurality of sub-pixels are divided into a plurality of pixel units; a pixel unit includes at least three sub-pixels arranged in sequence in the first direction; and the plurality of pixel units are arranged in a plurality of rows and a plurality of columns, pixel units in a row are arranged in the first direction and pixel units in a column are arranged in the second direction; and
a region between any two adjacent columns of pixel units is a first gap region.

6. The display panel according to claim 1 , wherein each sub-pixel region includes a sub-pixel circuit region for arranging a corresponding pixel drive circuit and a sub-pixel light-emitting region for arranging a corresponding light-emitting device that are arranged in the second direction;
in the second direction, the three adjacent rows of sub-pixel regions are the first row of sub-pixel regions, the second row of sub-pixel regions, and the third row of sub-pixel regions;
a region between the first row of sub-pixel regions and the second row of sub-pixel regions is a second gap region, and a region between the second row of sub-pixel regions and the third row of sub-pixel regions is a third gap region; wherein
in the first row of sub-pixel regions and the second row of sub-pixel regions, sub-pixel light-emitting regions are all closer to the second gap region than sub-pixel circuit regions; and
in the second row of sub-pixel regions and the third row of sub-pixel regions, sub-pixel circuit regions are all closer to the third gap region than sub-pixel light-emitting regions.

7. The display panel according to claim 6 , wherein the gate drive circuit further includes a plurality of transmission signal lines located in second gap regions and extending along the first direction;
two shift registers electrically connected to sub-pixels located in the first row of sub-pixel regions and sub-pixels located in the second row of sub-pixel regions share at least one of the plurality of transmission signal lines.

8. The display panel according to claim 7 , wherein the gate drive circuit further includes:
a first voltage signal line electrically connected to first voltage signal terminals of the two shift registers;
a second voltage signal line electrically connected to second voltage signal terminals of the two shift registers; and
a third voltage signal line electrically connected to third voltage signal terminals of the two shift registers; wherein
a transmission signal line of the plurality of transmission signal lines is the first voltage signal line, the second voltage signal line, or the third voltage signal line.

9. The display panel according to claim 7 , wherein at least one cascade input signal line includes a first input signal sub-line and a second input signal sub-line that are located in different first gap regions;
the gate drive circuit further includes an input signal connection line located in a second gap region and electrically connected to the first input signal sub-line and

Assignees

• Boe Technology Group Co Ltd

Inventors

• Han Ying
• Feng Xuehuan
• Lin Yicheng
• Xu Pan
• Wang Guoying
• Zhang Xing
• Gao Zhan
• Chu Mingi

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title