Display device and shift register circuit

Patent metadata

Field	Value
Publication number	US-10283063-B2
Application number	US-201715723218-A
Country	US
Kind code	B2
Filing date	Oct 3, 2017
Priority date	Oct 18, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

According to one embodiment, a display device includes a pixel circuit including first, second and third switches, a capacitor and an inverter, and a pixel electrode connected to the pixel circuit, the first switch including a first control electrode connected to a gate line and a first input terminal connected to a source line, the capacitor including a first terminal connected to a reference potential and a second terminal connected to the first output terminal, the third switch including a second input terminal and a second output terminal connected to the second terminal, and the second switch and the inverter being connected in series between the second terminal and the second input terminal.

First claim

What is claimed is:

1. A display device comprising:
a gate line arranged above a substrate along a first direction;
a source line arranged above the substrate along a second direction crossing the first direction;
a pixel circuit connected to the gate line and the source line and comprising a first switch, a second switch, a third switch, a capacitor and an inverter;
a pixel electrode connected to the pixel circuit, which supplies voltage to a display element,
the first switch being formed from an oxide semiconductor layer and comprising a first control electrode connected to the gate line and a first input terminal connected to the source line,
the capacitor comprising a first terminal connected to a reference potential and a second terminal connected to a first output terminal,
the third switch comprising a second input terminal and a second output terminal connected to the second terminal, and
the second switch and the inverter being connected in series between the second terminal and the second input terminal, wherein
the second switch comprises a p-type semiconductor layer and a second control electrode located on the p-type semiconductor layer,
the third switch comprises an oxide semiconductor layer located on the second control electrode and a third control electrode located on the oxide semiconductor layer,
an insulating film is located between the second control electrode and the oxide semiconductor layer, and
the second input terminal is located on the insulating film and in contact with the pixel electrode, and overlaps the p-type semiconductor layer.

2. The display device of claim 1 , wherein
the second switch comprises a third input terminal connected to the second terminal and a third output terminal, and
the inverter comprises a fourth input terminal connected to the third output terminal and a fourth output terminal connected to the second input terminal and the pixel electrode.

3. The display device of claim 2 , further comprising:
a first control line,
wherein
the second switch comprises a second control electrode connected to the first control line, and
the third switch comprises a third control electrode connected to the first control line.

4. The display device of claim 2 , further comprising:
a first control line and a second control line,
wherein
the second switch comprises a second control electrode connected to the first control line, and
the third switch comprises a third control electrode connected to the second control line.

5. The display device of claim 4 , wherein
the pixel circuit further comprises an auxiliary capacitor, and
the auxiliary capacitor comprises a third terminal connected to the reference potential and a fourth terminal connected to the third output terminal and the four input terminal.

6. The display device of claim 1 , wherein
the second switch comprises a third input terminal and a third output terminal connected to the second input terminal and the pixel electrode,
the inverter comprises a fourth input terminal connected to the second terminal and a fourth output terminal connected to the third input terminal.

7. The display device of claim 6 , further comprising:
a first control line,
wherein
the second switch comprises a second control electrode connected to the first control line, and
the third switch comprises a third control electrode connected to the first control line.

8. The display device of claim 1 , wherein
the third switch is formed directly above the second switch.

9. The display device of claim 1 , wherein
the second switch comprises a third output terminal located on the insulating film, and
the second input terminal is located between the third control electrode and the third output terminal.

10. The display device of claim 1 , wherein
the second output terminal is in contact with the p-type semiconductor layer via a contact hole which penetrates at least the insulating film.

11. A display device comprising:
a gate line arranged above a substrate along a first direction;
a source line arranged above the substrate along a second direction crossing the first direction;
a pixel circuit connected to the gate line and the source line and comprising a first switch, a second switch, a third switch, a capacitor and an inverter;
a pixel electrode connected to the pixel circuit, which supplies voltage to a display element;
the first switch being formed from an oxide semiconductor layer and comprising a first control electrode connected to the gate line and a first input terminal connected to the source line;
the capacitor comprising a first terminal connected to a reference potential and a second terminal connected to a first output terminal;
the third switch comprising a second input terminal and a second output terminal connected to the second terminal; and
the second switch and the inverter being connected in series between the second terminal and the second input terminal, wherein
the display element is an organic EL device,
the pixel circuit comprises a fourth switch, and
the fourth switch comprises a fifth input terminal connected to the second input terminal and a fifth output terminal connected to the pixel electrode.

Assignees

• Japan Display Inc

Inventors

• Aoki Yoshiro

Classifications

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title