Differentiable model for manufacturability

Patent metadata

Field	Value
Publication number	US-12287614-B2
Application number	US-202217665860-A
Country	US
Kind code	B2
Filing date	Feb 7, 2022
Priority date	Feb 7, 2022
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

Systems, computer-implemented methods, and instructions encoded in machine-accessible storage media are provided for determining manufacturability of an integrated circuit layout. A computer-implemented method includes receiving a layout describing the integrated circuit to be manufactured by a semiconductor manufacturing process. The method also includes generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter. The differentiable manufacturability parameter describes the manufacturability of the integrated circuit by the semiconductor manufacturing process.

First claim

What is claimed is:

1. A computer-implemented method for determining manufacturability of an integrated circuit, the method comprising:
receiving a layout describing the integrated circuit to be manufactured by a semiconductor manufacturing process; and
generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter, wherein the differentiable manufacturability parameter represents a continuous and differentiable function that describes the manufacturability of the integrated circuit by the semiconductor manufacturing process.

2. The computer implemented method of claim 1 , wherein generating the differentiable manufacturability parameter comprises:
segmenting the layout to define a patch;
generating a patch-level manufacturability parameter for the patch using the machine learning model; and
determining the differentiable manufacturability parameter using the patch-level manufacturability parameter.

3. The computer implemented method of claim 2 , wherein determining the manufacturability parameter comprises:
generating a plurality of patch-level manufacturability parameters including the patch-level manufacturability parameter; and
generating a product of the plurality of patch-level manufacturability parameters.

4. The computer implemented method of claim 2 , wherein the machine learning model is a convolutional neural network model, and wherein generating the patch-level manufacturability parameter comprises:
generating a patch image describing the patch;
inputting the patch image to the convolutional neural network model; and
generating the patch-level manufacturability parameter as an output of the convolutional neural network model.

5. The computer implemented method of claim 2 , wherein the patch describes a physical region of the integrated circuit.

6. The computer implemented method of claim 2 , wherein the patch describes a physical implementation of a logical function described by the layout and implemented by the integrated circuit.

7. The computer implemented method of claim 1 , further comprising training the machine learning model, the training comprising:
generating a training set of labeled data using a plurality of compliant and non-compliant designs, an entry of the training set comprising a training patch and a manufacturability label;
generating a training image of the training patch;
inputting the training image to the machine learning model;
generating a predicted manufacturability parameter as an output of the machine learning model;
generating a training signal using the predicted manufacturability parameter and the manufacturability label; and
modifying one or more learned parameters of the machine learning model using the training signal.

8. The computer implemented method of claim 7 , further comprising:
generating a simulated manufacturability parameter for the training patch using a process model describing one or more constituent processes of the semiconductor manufacturing system, wherein generating the training signal further uses the simulated manufacturability parameter.

9. The computer implemented method of claim 1 , further comprising:
receiving an optimization criterion; and
modifying one or more elements of the layout based at least in part on the optimization criterion,
wherein the optimization criterion describes a target manufacturability value, and wherein an extent of modifying the one or more elements of the layout is determined using a gradient-based optimization method and the differentiable manufacturability parameter.

10. The computer implemented method of claim 9 , wherein the optimization criterion is a part of a set of optimization criteria for the integrated circuit layout including a target power value, a target performance value, a target area value, or combinations thereof, the computer-implemented method further comprising:
generating an optimization factor describing the performance of the layout against the set of optimization criteria, wherein the extent of modifying the one or more elements of the layout is determined using the optimization factor.

11. The computer implemented method of claim 1 , further comprising:
determining a wafer-scale yield of the semiconductor manufacturing process using the differentiable manufacturability parameter.

12. The computer implemented method of claim 11 , wherein determining the wafer-scale yield comprises:
generating a map of wafer-scale variation of manufacturability using a process model provided with process data describing one or more constituent processes of semiconductor manufacturing process; and
determining the wafer-scale yield using the map of waver-scale variation, wherein the variation described a deviation of manufacturability as a function of position on a surface of a wafer.

13. At least one machine-accessible storage medium that provides instructions that, when executed by a machine, will cause the machine to perform operations comprising:
receiving a layout describing an integrated circuit to be manufactured by a semiconductor manufacturing process; and
generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter, wherein the differentiable manufacturability parameter represents a continuous and differentiable function that describes the manufacturability of the integrated circuit by the semiconductor manufacturing process.

14. The machine-accessible storage medium of claim 13 , wherein generating the differentiable manufacturability parameter comprises:
segmenting the layout to define a patch;
generating a patch-level manufacturability parameter for the patch using the machine learning model; and
determining the differentiable manufacturability parameter using the patch-level manufacturability parameter.

15. The machine-accessible storage medium of claim 14 , wherein the differentiable manufacturability parameter comprises:
generating a plurality of patch-level manufacturability parameters including the patch-level manufacturability parameter; and
generating a product of the plurality of patch-level manufacturability parameters.

16. The machine-accessible storage medium of claim 15 , wherein the machine learning model is a convolutional neural network model, and wherein generating the patch-level manufacturability parameter comprises:
generating a patch image describing the patch;
inputting the patch image to the convolutional neural network model; and
predicting the patch-level manufacturability parameter as an output of the convolutional neural network model.

17. A machine-accessible storage medium that provides instructions that, when executed by a machine, with cause the machine to perform operations comprising:
receiving a layout describing an integrated circuit to be manufactured by a semiconductor manufacturing process;
receiving identifier data with the layout, the identifier data identifying the semiconductor manufacturing process;
generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter, wherein the differentiable manufacturability parameter describes the manufacturability of the integrated circuit by the semiconductor manufacturing process; a

Assignees

• X Dev Llc

Inventors

• Apte Raj
• Behroozi Cyrus
• Pan Zhigang
• Ruic Dino

Classifications

• G05B13/0265

  the criterion being a learning criterion · CPC title

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G05B19/188 Primary

  characterised by special applications and not provided for in the relevant subclasses, (e.g. making dies, filament winding) · CPC title