Rule check violation prediction systems and methods

Patent metadata

Field	Value
Publication number	US-10943049-B2
Application number	US-201916400664-A
Country	US
Kind code	B2
Filing date	May 1, 2019
Priority date	Sep 28, 2018
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

First claim

The invention claimed is:

1. A systematic design rule check (DRC) violation prediction system, comprising:
DRC machine learning circuitry configured to generate information associated with a plurality of routing congestion patterns, based on past data indicative of presence and location of DRC violations in placement layouts after routing has been performed, the plurality of routing congestion patterns including regions where a plurality of systematic DRC violations are predicted or determined to occur;
DRC violation prediction circuitry, which, when in use:
receives placement data associated with a placement layout;
inspects the placement data associated with the placement layout; and
predicts, prior to routing the placement layout, whether one or more systematic DRC violations would be caused by routing congestion due to the subsequent routing of the placement layout, based at least in part on the information associated with the plurality of routing congestion patterns; and a placement database which stores the placement data associated with the placement layout.

2. The system of claim 1 , further comprising:
a processed pattern database which stores the information associated with the plurality of routing congestion patterns.

3. The system of claim 2 , further comprising:
a systematic DRC database which stores information associating systematic DRC violations with at least one of a placement layout or a placement layout region,
wherein the DRC machine learning circuitry is communicatively coupled to the systematic DRC database and to the processed pattern database, the DRC machine learning circuitry, when in use, generates the information associated with the plurality of routing congestion patterns based on the information stored in the systematic DRC database.

4. The system of claim 2 wherein the information stored in the processed pattern database includes probability information indicating probabilities of one or more systematic DRC violations occurring in the plurality of routing congestion patterns.

5. The system of claim 4 wherein the DRC machine learning circuitry, when in use, generates the probability information by performing a probability mass function transformation on the information stored in the systematic DRC database.

6. The system of claim 5 wherein the DRC machine learning circuitry, when in use, identifies systematic DRC clusters in the processed patterns based on the probability information.

7. The system of claim 6 wherein the DRC machine learning circuitry, when in use, identifies the systematic DRC clusters in the processed patterns based on a cosine similarity between one or more features in the processed patterns.

8. The system of claim 6 wherein the systematic DRC violation prediction circuitry, when in use:
identifies a cluster of predicted systematic DRC violations in the placement layout based on the identified systematic DRC clusters in the processed patterns.

9. The system of claim 8 wherein the systematic DRC violation prediction circuitry, when in use:
generates a bounding box surrounding the identified cluster of predicted systematic DRC violations in the placement layout; and
determines a location of the one or more systematic DRC violations in the placement layout based on the bounding box.

10. The system of claim 1 , further comprising:
density control circuitry, which, when in use increases a spacing between cells of a region of the placement layout, in response to the DRC violation prediction circuitry predicting that one or more systematic DRC violations would be present in the region of the placement layout due to the subsequent routing of the placement layout.

11. An electronic device design system, comprising:
an electronic design platform including a placement tool configured to generate a placement layout; and
a routing congestion removal platform, including:
DRC machine learning circuitry configured to generate information associated with a plurality of routing congestion patterns, based on past data indicative of presence and location of DRC violations in placement layouts after routing has been performed, the plurality of routing congestion patterns including, regions where a plurality of systematic DRC violations are predicted or determined to occur, and
a design rule check (DRC) violation prediction tool configured to:
receive placement data associated with the placement layout;
inspect the placement data associated with the placement layout; and
predict, prior to routing the placement layout, whether one or more systematic DRC violations would be caused by routing congestion due to the subsequent routing of the placement layout, based at least in part on the information associated with the plurality of routing congestion patterns, wherein the DRC violation prediction tool includes a placement database configured to store the placement data associated with the placement layout.

12. The system of claim 11 , wherein the DRC violation prediction tool includes:
a processed pattern database configured to store the information associated with the plurality of routing congestion patterns.

13. The system of claim 12 , wherein the DRC violation prediction tool includes:
a systematic DRC database which stores information associating systematic DRC violations with at least one of a placement layout or a placement layout region
wherein the DRC machine learning circuitry is communicatively coupled to the systematic DRC database and to the processed pattern database, the DRC machine learning circuitry, when in use, generates the information associated with the plurality of routing congestion patterns based on the information stored in the systematic DRC database.

14. The system of claim 11 , wherein the routing congestion removal platform includes a density control tool, the density control tool including:
density control circuitry configured to increase a spacing between cells of a region of the placement layout, in response to the DRC violation prediction tool predicting that one or more systematic DRC violations would be present in the region of the placement layout due to the subsequent routing of the placement layout.

15. The system of claim 14 , wherein the electronic design platform includes a routing tool configured to perform the routing of the placement layout.

16. An electronic device design system, comprising:
an electronic design platform, including:
a placement tool configured to generate a placement layout; and
a feature extraction tool configured to extract information associated with one or more features of the placement layout; and

a routing congestion removal platform including:
DRC machine learning, circuitry configured to generate information associated with a plurality of routing congestion patterns, based on past data indicative of presence and location of DRC violations in placement layouts after routing has been performed, the plurality of routing congestion patterns including regions where a plurality of systematic DRC violations are predicted or determined to occur;
a design rule check (DRC) violation prediction tool configured to:
receive placement data associated with the placement layout;
inspect the placement data associated with the placement layout, the placement data including the extracted information associated with one or more features of the placement layout; and
predict, prior to routing the placement layout, whether one or more systematic DRC violations would be caused by routing congestion due to the subsequent routing of the placement layout, based at least in part on

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Yi-Lin
• Lin Henry
• Huang Szu-Ju
• Chen Yin-An
• Hong Amos

Classifications

• G06N20/00

  Machine learning · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title