Fin end plug structures for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-12284826-B2
Application number	US-202418412236-A
Country	US
Kind code	B2
Filing date	Jan 12, 2024
Priority date	Nov 30, 2017
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin along a direction;
a first isolation structure at and in contact with a first end of the fin, wherein the first isolation structure has a top surface above the top of the fin;
a gate structure comprising a gate electrode over a channel region of the fin, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
a second isolation structure at and in contact with a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction, wherein the second isolation structure has a top surface above the top of the fin, and wherein the first isolation structure and the second isolation structure each comprise a first dielectric material having a lower portion laterally surrounding a second dielectric material, the second dielectric material laterally surrounding at least a portion of a third dielectric material, and a fourth dielectric material above the second dielectric material and the third dielectric material, the four dielectric material laterally surrounded by an upper portion of the first dielectric material.

2. The integrated circuit structure of claim 1 , wherein the third dielectric material has an uppermost surface at a same level as an uppermost surface of the second dielectric material.

3. The integrated circuit structure of claim 1 , wherein the third dielectric material has an uppermost surface above an uppermost surface of the second dielectric material.

4. The integrated circuit structure of claim 1 , wherein the third dielectric material has an uppermost surface below an uppermost surface of the second dielectric material.

5. The integrated circuit structure of claim 1 , wherein the fourth dielectric material has an approximately vertical central seam.

6. The integrated circuit structure of claim 1 , wherein the fourth dielectric material does not have a seam.

7. The integrated circuit structure of claim 1 , wherein the first and second isolation structures induce a compressive stress on the fin.

8. The integrated circuit structure of claim 7 , wherein the gate electrode is a P-type gate electrode.

9. The integrated circuit structure of claim 1 , wherein the first and second isolation structures induce a tensile stress on the fin.

10. The integrated circuit structure of claim 9 , wherein the gate electrode is an N-type gate electrode.

11. An integrated circuit structure, comprising:
a nanowire along a direction;
a first isolation structure at and in contact with a first end of the nanowire, wherein the first isolation structure has a top surface above the top of the nanowire;
a gate structure comprising a gate electrode completely surrounding a channel region of the nanowire, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
a second isolation structure at and in contact with a second end of the nanowire, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction, wherein the second isolation structure has a top surface above the top of the nanowire, and wherein the first isolation structure and the second isolation structure each comprise a first dielectric material having a lower portion laterally surrounding a second dielectric material, the second dielectric material laterally surrounding at least a portion of a third dielectric material, and a fourth dielectric material above the second dielectric material and the third dielectric material, the four dielectric material laterally surrounded by an upper portion of the first dielectric material.

12. The integrated circuit structure of claim 11 , wherein the third dielectric material has an uppermost surface at a same level as an uppermost surface of the second dielectric material.

13. The integrated circuit structure of claim 11 , wherein the third dielectric material has an uppermost surface above an uppermost surface of the second dielectric material.

14. The integrated circuit structure of claim 11 , wherein the third dielectric material has an uppermost surface below an uppermost surface of the second dielectric material.

15. The integrated circuit structure of claim 11 , wherein the fourth dielectric material has an approximately vertical central seam.

16. The integrated circuit structure of claim 11 , wherein the fourth dielectric material does not have a seam.

17. The integrated circuit structure of claim 11 , wherein the first and second isolation structures induce a compressive stress on the nanowire.

18. The integrated circuit structure of claim 17 , wherein the gate electrode is a P-type gate electrode.

19. The integrated circuit structure of claim 11 , wherein the first and second isolation structures induce a tensile stress on the nanowire.

20. The integrated circuit structure of claim 19 , wherein the gate electrode is an N-type gate electrode.

Assignees

• Intel Corp

Inventors

• Ho Byron
• Huang Chun-Kuo
• Thompson Erica
• Luce Jeanne
• Hattendorf Michael L
• Auth Christopher P
• Mays Ebony L

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0193

  the components including FinFETs · CPC title