Fin end plug structures for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-11380683-B2
Application number	US-202017076425-A
Country	US
Kind code	B2
Filing date	Oct 21, 2020
Priority date	Nov 30, 2017
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction;
a first isolation structure over a first end of the fin, wherein a portion of the first isolation structure is on a first portion of the top and sidewalls of the fin, and wherein the first isolation structure has a top surface above the top of the fin;
a gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of a region of the fin, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
a second isolation structure over a second end of the fin, the second end opposite the first end, wherein a portion of the second isolation structure is on a second portion of the top and sidewalls of the fin, the second isolation structure spaced apart from the gate structure along the direction, wherein the second isolation structure has a top surface above the top of the fin, wherein the first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a second dielectric material distinct from the first dielectric material, the second dielectric material having an upper surface, and wherein the wherein the first isolation structure and the second isolation structure both further comprise a third dielectric material laterally surrounded by an upper portion of the first dielectric material, the third dielectric material on the upper surface of the second dielectric material, the third dielectric material distinct from the first dielectric material and from the second dielectric material.

2. The integrated circuit structure of claim 1 , wherein the third dielectric material has an approximately vertical central seam.

3. The integrated circuit structure of claim 1 , wherein the third dielectric material does not have a seam.

4. The integrated circuit structure of claim 1 , wherein the first and second isolation structures induce a compressive stress on the fin.

5. The integrated circuit structure of claim 4 , wherein the gate electrode is a P-type gate electrode.

6. The integrated circuit structure of claim 1 , wherein the first isolation structure has a width along the direction, the gate structure has the width along the direction, and the second isolation structure has the width along the direction.

7. The integrated circuit structure of claim 6 , wherein a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the direction, and a center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the direction.

8. The integrated circuit structure of claim 1 , wherein the first and second isolation structures are both in a corresponding trench in an inter-layer dielectric layer.

9. The integrated circuit structure of claim 1 , further comprising:
a first source or drain region between the gate structure and the first isolation structure; and
a second source or drain region between the gate structure and the second isolation structure.

10. The integrated circuit structure of claim 9 , wherein the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium.

11. The integrated circuit structure of claim 1 , the gate structure further comprising a high-k dielectric layer between the gate electrode and the fin and along sidewalls of the gate electrode.

12. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction;
a first isolation structure over a first end of the fin, wherein a portion of the first isolation structure is on a first portion of the top and sidewalls of the fin, and wherein the first isolation structure has a top surface above the top of the fin;
a gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of a region of the fin, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
a second isolation structure over a second end of the fin, the second end opposite the first end, wherein a portion of the second isolation structure is on a second portion of the top and sidewalls of the fin, the second isolation structure spaced apart from the gate structure along the direction, wherein the second isolation structure has a top surface above the top of the fin, wherein the first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a second dielectric material distinct from the first dielectric material, the second dielectric material having an upper surface, and wherein the wherein the first isolation structure and the second isolation structure both further comprise a third dielectric material laterally surrounded by an upper portion of the first dielectric material, the third dielectric material on the upper surface of the second dielectric material, the third dielectric material distinct from the first dielectric material and from the second dielectric material.

13. The computing device of claim 12 , further comprising:
a memory coupled to the board.

14. The computing device of claim 12 , further comprising:
a communication chip coupled to the board.

15. The computing device of claim 12 , further comprising:
a camera coupled to the board.

16. The computing device of claim 12 , further comprising:
a battery coupled to the board.

17. The computing device of claim 12 , further comprising:
an antenna coupled to the board.

18. The computing device of claim 12 , wherein the component is a packaged integrated circuit die.

19. The computing device of claim 12 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

20. The computing device of claim 12 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Assignees

• Intel Corp

Inventors

• Ho Byron
• Huang Chun-Kuo
• Thompson Erica
• Luce Jeanne
• Hattendorf Michael L
• Auth Christopher P
• Mays Ebony L

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0193

  the components including FinFETs · CPC title