Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12284809-B2
Application number	US-202217737479-A
Country	US
Kind code	B2
Filing date	May 5, 2022
Priority date	Dec 17, 2021
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

A semiconductor memory device, and a method of manufacturing the same, includes a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked on a substrate in a vertical direction, a channel structure penetrating at least a portion of the gate stacked body and having a first end protruding upward higher than the gate stacked body, a memory layer enclosing a sidewall of the channel structure, and a source layer formed on the gate stacked body. The channel structure includes a core insulating layer formed in a central region of the channel structure and extending in a vertical direction, and a channel layer enclosing a sidewall of the core insulating layer and formed to be higher than the core insulating layer and the memory layer in the vertical direction.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked on a substrate in a vertical direction;
a channel structure penetrating at least a portion of the gate stacked body and having a first end protruding upward higher than the gate stacked body;
a memory layer enclosing a sidewall of the channel structure; and
a source layer formed on the gate stacked body,
wherein the channel structure comprises:
a core insulating layer formed in a central region of the channel structure and extending in a vertical direction; and
a channel layer enclosing a sidewall of the core insulating layer and formed to be higher than the core insulating layer and the memory layer in the vertical direction.

2. The semiconductor memory device according to claim 1 , wherein an uppermost portion of the channel structure includes an opening defined by the channel layer protruding higher than the core insulating layer.

3. The semiconductor memory device according to claim 2 , wherein the source layer comprises:
a first source layer formed along an upper portion of the gate stacked body and a surface of the protruding first end of the channel structure; and
a second source layer formed on the first source layer.

4. The semiconductor memory device according to claim 3 , wherein the first source layer and the second source layer are formed to fill the opening.

5. The semiconductor memory device according to claim 3 , wherein the source layer further comprises a third source layer formed on the second source layer.

6. The semiconductor memory device according to claim 5 , wherein:
the first source layer includes a doped polysilicon layer,
the second source layer includes a titanium layer or a titanium nitride layer, and
the third source layer includes a tungsten layer.

7. The semiconductor memory device according to claim 3 , wherein:
the channel layer includes a protrusion protruding upward higher than the core insulating layer and the memory layer, and
the first source layer is directly coupled to the protrusion of the channel layer.

8. The semiconductor memory device according to claim 3 , further comprising a sacrificial substrate disposed between the first source layer and the gate stacked body.

9. A semiconductor memory device, comprising:
a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked on a substrate in a vertical direction;
a sacrificial substrate formed on the gate stacked body;
a channel structure penetrating at least a portion of the gate stacked body and the sacrificial substrate, the channel structure having a first end protruding upward from the sacrificial substrate;
a memory layer enclosing a sidewall of the channel structure; and
a source layer formed on the gate stacked body,
wherein the protruding first end of the channel structure includes an opening.

10. The semiconductor memory device according to claim 9 , wherein the channel structure comprises:
a core insulating layer formed in a central region of the channel structure and extending in a vertical direction; and
a channel layer enclosing a sidewall of the core insulating layer and formed to be higher than the core insulating layer and the memory layer in the vertical direction.

11. The semiconductor memory device according to claim 10 , wherein:
the channel layer includes a protrusion protruding upward higher than the core insulating layer and the memory layer, and
the source layer is directly coupled to the protrusion of the channel layer.

12. The semiconductor memory device according to claim 11 , wherein the opening is defined by the protrusion of the channel layer and an upper portion of the core insulating layer.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title