Network device with programmable action processing

Patent metadata

Field	Value
Publication number	US-12282775-B2
Application number	US-202318321013-A
Country	US
Kind code	B2
Filing date	May 22, 2023
Priority date	May 22, 2023
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.

First claim

The invention claimed is:

1. A network device, comprising:
one or more ports, to exchange packets between the network device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and
an instruction processor, to perform the programmable action by running user-programmable software code,
wherein the instruction processor comprises architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and
wherein the match-action circuitry is to write into the architectural registers information for performing the programmable action, the information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action.

2. The network device according to claim 1 , wherein the match-action circuitry is to instruct the instruction processor to perform the programmable action using the information written into the architectural registers.

3. The network device according to claim 1 , wherein the match-action circuitry is to perform one or more of the actions that are non-programmable.

4. The network device according to claim 1 , wherein the match-action circuitry is to distinguish between programmable actions and non-programmable actions, and to trigger the instruction processor to perform the programmable actions.

5. The network device according to claim 1 , wherein the instruction processor comprises one or more Reduced Instruction Set Computer (RISC) cores.

6. The network device according to claim 1 , wherein the instruction processor comprises an internal memory, and is to run the user-programmable code entirely from the internal memory.

7. The network device according to claim 1 , wherein the instruction processor is to run the user-programmable code from an external memory, using an instruction cache that is to cache instructions of the user-programmable code.

8. A network device, comprising:
one or more ports, to exchange packets between the network device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and
an instruction processor, to perform the programmable action by running user-programmable software code,
wherein the instruction processor comprises architectural registers, one or more of the architectural registers being accessible by the match-action circuitry,
wherein the match-action circuitry is to write into the architectural registers information for performing the programmable action,
wherein the instruction processor comprises an execution pipeline to run the user-programmable software code, and wherein the match-action circuitry is to trigger the execution pipeline after writing state information to the architectural registers.

9. The network device according to claim 8 , wherein the execution pipeline supports Arithmetic Logic Unit (ALU) operations and flow-control operations, but does not support memory load and store operations.

10. The network device according to claim 8 , wherein the execution pipeline supports memory load and store operations.

11. A method, comprising:
exchanging packets between a network device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the network device, so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and
performing the programmable action by running user-programmable software code on an instruction processor in the network device, including writing, by the match-action circuitry, information for performing the programmable action into one or more architectural registers of the instruction processor that are accessible by the match-action circuitry, the information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action.

12. The method according to claim 11 , and comprising, using the match-action circuitry, distinguishing between programmable actions and non-programmable actions, and triggering the instruction processor to perform the programmable actions.

13. A method, comprising:
exchanging packets between a network device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the network device, so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and
performing the programmable action by running user-programmable software code on an instruction processor in the network device, including writing, by the match-action circuitry, information for performing the programmable action into one or more architectural registers of the instruction processor that are accessible by the match-action circuitry,
wherein performing the programmable action comprises, using the match-action circuitry, triggering an execution pipeline of the instruction processor after writing state information to the architectural registers.

14. The method according to claim 13 , wherein the execution pipeline supports Arithmetic Logic Unit (ALU) operations and flow-control operations, but does not support memory load and store operations.

15. A network device, comprising:
one or more ports, to exchange packets between the network device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory; and
an instruction processor, to perform the stateful programmable action by running user-programmable software code,
wherein the instruction processor comprises architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and
wherein the match-action circuitry is to retrieve the state information from the memory and to write the retrieved state information into the architectural registers, for performing the stateful programmable action.

16. The network device according to claim 15 , wherein, following the completion of the stateful programmable action, the match-action circuitry is to read updated state information from the architectural registers and to save the updated state information in the memory.

17. A method, comprising:
exchanging packets between a network device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the network device, so as to set respective actions to be performed, wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory;
using the match-action circuitry, retrieving the state information from the memory and writing the retrieved state information into one or more architectural registers of an instruction processor in the network device, for performing the programmable action; and
performing the stateful programmable action by running the user-programmable software code on the instruction processor.

18. The method according to claim 17 , and comprising, following completion of the stateful action, reading updated state information from the architectural registers b

Assignees

• Mellanox Technologies Ltd

Inventors

• Shahar Ariel
• Urman Avi
• Kahalon Omri
• Basher Uria
• Haim Doron
• Farjun Sagi

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• H04L41/082

  the condition being updates or upgrades of network functionality · CPC title

• H04L41/0803 Primary

  Configuration setting · CPC title