Flexible cryptographic architecture in a network device
US-2026006010-A1 · Jan 1, 2026 · US
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Basher Uria patents
Basher Uria is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Basher Uria |
| Total patents | 27 |
| First publication | Mar 7, 2019 |
| Latest publication | Jan 1, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Duplicate write circuit
US-12498879-B2 · Dec 16, 2025 · US
Maintaining data confidentiality in shared computing environments
US-2025363203-A1 · Nov 27, 2025 · US
Network device with datagram transport layer security selective software offload
US-12452219-B2 · Oct 21, 2025 · US
Flexible cryptographic architecture in a network device
US-12438859-B2 · Oct 7, 2025 · US
Duplicate Write Circuit
US-2025298537-A1 · Sep 25, 2025 · US
Maintaining data confidentiality in shared computing environments
US-12417278-B2 · Sep 16, 2025 · US
Network Device with Programmable Action Processing
US-2025217148-A1 · Jul 3, 2025 · US
Confidential computing with device memory isolation
US-2025190544-A1 · Jun 12, 2025 · US
Network device with programmable action processing
US-12282775-B2 · Apr 22, 2025 · US
Recent patents
Latest publications not already listed above.
Confidential computing with device memory isolation
US-12259963-B2 · Mar 25, 2025 · US
Network device with datagram transport layer security selective software offload
US-2024406148-A1 · Dec 5, 2024 · US
Native link encryption
US-2024406154-A1 · Dec 5, 2024 · US
Network Device with Programmable Action Processing
US-2024394060-A1 · Nov 28, 2024 · US
Efficient montgomery multiplier
US-12131132-B2 · Oct 29, 2024 · US
Fast precomputation for Montgomery multiplier
US-12079594-B2 · Sep 3, 2024 · US
Maintaining data confidentiality in shared computing environments
US-2024202315-A1 · Jun 20, 2024 · US
Flexible cryptographic architecture in a network device
US-2024146703-A1 · May 2, 2024 · US
Confidential Computing with Device Memory Isolation
US-2023267196-A1 · Aug 24, 2023 · US
Network adapter with efficient storage-protocol emulation
US-11726666-B2 · Aug 15, 2023 · US
Network Adapter with Efficient Storage-Protocol Emulation
US-2023010150-A1 · Jan 12, 2023 · US
Fast Precomputation for Montgomery Multiplier
US-2022269488-A1 · Aug 25, 2022 · US
Efficient Montgomery Multiplier
US-2022269487-A1 · Aug 25, 2022 · US
Code sequencer that, in response to a primary processing unit encountering a trigger instruction, receives a thread identifier, executes predefined instruction sequences, and offloads computations to at least one accelerator
US-10599441-B2 · Mar 24, 2020 · US
Timing-adaptive, configurable logic architecture
US-10565339-B2 · Feb 18, 2020 · US
Timing-adaptive, configurable logic architecture
US-2020026814-A1 · Jan 23, 2020 · US
Code Sequencer
US-2019073217-A1 · Mar 7, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Mellanox Technologies Ltd | 26 |
| Nvidia Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F21/602 | 7 |
| G06F21/53 | 6 |
| H04L63/0485 | 5 |
| G06F9/5077 | 5 |
| G06F21/575 | 4 |