Balancing power, endurance and latency in a ferroelectric memory

Patent metadata

Field	Value
Publication number	US-12282681-B2
Application number	US-202217841083-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Jun 17, 2021
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

First claim

What is claimed is:

1. A method comprising:
receiving a data set for storage to a non-volatile memory (NVM) comprising an array of ferroelectric memory cells (FMEs); and
programming the data set to a group of the FMEs at a target location in the NVM using a selected profile to balance power, endurance and latency associated with the data set, the selected profile retrieved from a memory that stores an additional number of different profiles for the group of the FMEs at the target location for different combinations of power, endurance and latency,
wherein the selected profile is selected from a plurality of profiles stored in a local memory, each of the plurality of profiles associated with a different physical location within the NVM, and
wherein different profiles are applied to program the data based on different location of the FME on the NVM, such that a first profile applied to program the data for the FME incorporated in a main memory is different than a second profile applied to program the data for the FME incorporated in a cache memory.

2. The method of claim 1 , wherein the selected profile comprises a magnitude and duration of applied power to each of the FMEs in the group of FMEs at the target location within the NVM to achieve a specified endurance in terms of an overall data retention time for the data set meeting or exceeding a selected endurance threshold.

3. The method of claim 2 , wherein the magnitude and duration of applied power are further selected to achieve an average latency during a subsequent read operation that meets or exceeds a predetermined latency threshold.

4. The method of claim 1 , wherein the FMEs are each characterized as at least a selected one of ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM) memory cells each having at least one transistor and at least one capacitor, or ferroelectric field effect transistors (FeFETs).

5. The method of claim 1 , further comprising subsequently reading the data set from the target location in the NVM using a second selected profile associated with at least a selected one of the data set or the target location.

6. The method of claim 1 , wherein the first profile applied to program the data for the FME incorporated in a main memory is specified for long term storage of data compared to the second profile applied to program the data for the FME incorporated in the cache memory.

7. The method of claim 1 , wherein the data set is received from a client with a write command to store the data set to the NVM with an associated logical address, and wherein the selected profile is based on a determination of a frequency of other commands received from the client to transfer data for the associated logical address.

8. The method of claim 1 , further comprising subsequently retrieving the data set from the NVM, performing an error correction operation upon the retrieved data set to correct at least one bit error, and subsequently writing a second data set to the NVM using a second selected profile based on the error correction operation.

9. The method of claim 1 , further comprising selecting the selected profile responsive to a data characteristic of the data set, wherein a larger amount of power is used responsive to the data set characterized as a cold data set requiring longer data retention, and wherein a smaller amount of power is used responsive to the data set characterized as a hot data set requiring shorter data retention.

10. The method of claim 1 , wherein the selected profile is selected responsive to a total amount of wear in terms of program counts of the target location of the NVM to which the data set is to be written.

11. The method of claim 1 , wherein the selected profile is selected responsive to a construction type of the FMEs to which the data set is written.

12. The method of claim 1 , wherein the NVM is characterized as a selected one of a write cache, a read buffer, a local processor memory, or a main memory store of a solid-state drive (SSD).

13. The method of claim 1 , wherein the NVM is a stack register which forms a portion of a data storage device, the data storage device having a main memory store to store user data from a client device.

14. An apparatus, comprising:
a non-volatile memory (NVM) comprising ferroelectric memory elements (FMEs);
read/write (R/W) circuitry configured to respectively write data to and read data from the FMEs;
a local memory which stores a plurality of profiles for the R/W circuitry associated with different combinations of power, endurance and latency, wherein each of the plurality of profiles associated with a different physical location within the NVM; and
a controller circuit configured to receive a data set from an external client device and to forward a selected profile from the local memory to the R/W circuitry to write the data set to a group of the FMEs at a target location in the NVM, the selected profile operative to balance power, endurance and latency associated with the data set, and
wherein different profiles are applied to program the data based on different location of the FME on the NVM.

15. The apparatus of claim 14 , wherein the selected profile comprises a magnitude and duration of applied power to each of the FMEs at the target location to achieve a specified endurance in terms of an overall data retention time for the data set meeting or exceeding a predetermined endurance threshold and to achieve an average latency during a subsequent read operation that meets or exceeds a predetermined latency threshold.

16. The apparatus of claim 14 , wherein the selected profile is a first selected profile, the controller circuit is further configured to configure the R/W circuitry to subsequently read the data set from the group of FMEs at the target location using a second selected profile stored in the local memory and associated with at least a selected one of the data set or the target location, and the second selected profile is based on the first selected profile.

17. The apparatus of claim 14 , wherein the data set has an associated logical address, and wherein the selected profile is based on a determination of a frequency of other commands received from the client device to transfer data sets having the associated logical address.

18. The apparatus of claim 14 , wherein the controller circuit is further configured to direct the R/W circuit to subsequently retrieve the data set from the NVM, perform an error correction operation upon the retrieved data set to correct at least one bit error, and subsequently rewrite the data set to the NVM using a second selected profile provided to the R/W circuit by the controller circuit based on the error correction operation.

19. The apparatus of claim 14 , wherein the FMEs are each characterized as at least a selected one of ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM) memory cells each having at least one transistor and at least one capacitor, or ferroelectric field effect transistors (FeFETs).

20. The apparatus of claim 14 , wherein different profiles are associated with signal loss effects at the physical location of the NVM.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Viraraghavan Praveen
• Dykes John W
• Gilbert Ian J
• Kalarickal Sangita Shreedharan
• Totin Matthew J
• El-Batal Mohamad
• Mehta Darshana H

Classifications

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title