Hardware-assisted core frequency and voltage scaling in a poll mode idle loop

Patent metadata

Field	Value
Publication number	US-12282377-B2
Application number	US-202117358224-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

First claim

What is claimed is:

1. A hardware controller within a core of a processor to adjust power settings of the core, the hardware controller comprising:
telemetry logic to generate telemetry data that indicates an activity state of the core,
wherein the telemetry data includes one or more of (1) a number of branch hits and (2) a number of branch misses;

core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state, wherein the core stall detection logic is to determine the core is in the idle loop state by calculating a branch miss-to-hit ratio over a time period and based on a set of thresholds, wherein the core stall detection logic is to calculate the branch miss-to-hit ratio using a hardware counter and set an increment level and a decrement level for the hardware counter based on the set of thresholds; and
a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

2. The hardware controller of claim 1 , wherein the core stall detection logic is to (1) increment the hardware counter by the increment level in response to the telemetry data indicating a branch hit occurred in the core and (2) decrement the hardware counter by the decrement level in response to the telemetry data indicating a branch miss occurred in the core.

3. The hardware controller of claim 1 , wherein the power controller is to receive the telemetry data from the telemetry logic and is to determine, based on the telemetry data from the telemetry logic, whether the core is in the idle loop state.

4. The hardware controller of claim 3 , wherein the power controller is to, in response to the core stall detection logic determining that the core is not in the idle loop state, raise the power mode of the core from a second mode associated with the second set of power settings to a first mode associated with the first set of power settings.

5. The hardware controller of claim 1 , wherein the idle loop state includes the core polling an address to determine whether a packet has been received for processing by the core.

6. A method performed by a hardware controller within a core of a processor to adjust power settings of the core, the method comprising:
generating, by the hardware controller, telemetry data that indicates an activity state of the core, wherein the telemetry data includes one or more of (1) a number of branch hits and (2) a number of branch misses;
determining, by the hardware controller, based on the telemetry data whether the core is in an idle loop state, wherein the hardware controller is to determine the core is in the idle loop state by calculating a branch miss-to-hit ratio over a time period and based on a set of thresholds, wherein the hardware controller is to calculate the branch miss-to-hit ratio using a hardware counter;
setting, by the hardware controller, an increment level and a decrement level for the hardware counter based on the set of thresholds; and
decreasing, by the hardware controller in response to determining that the core is in the idle loop state, a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

7. The method of claim 6 , further comprising:
incrementing, by the hardware controller, the hardware counter by the increment level in response to the telemetry data indicating a branch hit occurred in the core; and
decrementing, by the hardware controller, the hardware counter by the decrement level in response to the telemetry data indicating a branch miss occurred in the core.

8. The method of claim 6 , further comprising:
increasing, by the hardware controller in response to determining that the core is not in the idle loop state, the power mode of the core from a second mode associated with the second set of power settings to a first mode associated with the first set of power settings.

9. The method of claim 6 , wherein the idle loop state includes the core polling an address to determine whether a packet has been received for processing by the core.

10. A non-transitory computer readable medium that stores instructions, which when executed by a hardware controller of a core, cause the hardware controller to:
generate telemetry data that indicates an activity state of the core, wherein the telemetry data includes one or more of (1) a number of branch hits and (2) a number of branch misses;
determine based on the telemetry data whether the core is in an idle loop state, wherein
the hardware controller is to determine the core is in the idle loop state by calculating a branch miss-to-hit ratio over a time period and based on a set of thresholds, wherein the hardware controller is to calculate the branch miss-to-hit ratio using a hardware counter;

set an increment level and a decrement level for the hardware counter based on the set of thresholds;
increment the hardware counter by the increment level in response to the telemetry data indicating a branch hit occurred in the core; and
decrease, in response to determining that the core is in the idle loop state, a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

11. The non-transitory computer readable medium of claim 10 , wherein the instructions further cause the hardware controller to:
increase, in response to determining that the core is not in the idle loop state, the power mode of the core from a second mode associated with the second set of power settings to a first mode associated with the first set of power settings.

Assignees

• Intel Corp

Inventors

• Shah Pritesh P
• Chemudupati Suresh
• Gendler Alexander
• Hunt David
• Macnamara Christopher M
• Nathan Ofer
• Purandare Adwait
• Varma Ankush

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/324

  by lowering clock frequency · CPC title