Semiconductor apparatus having expansion wires for electrically connecting chips

Patent metadata

Field	Value
Publication number	US-12278243-B2
Application number	US-202117529969-A
Country	US
Kind code	B2
Filing date	Nov 18, 2021
Priority date	Mar 12, 2021
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a plurality of chips arranged on the base substrate each including a chip main body and a plurality of terminals arranged thereon; a plurality of fixed connection portions arranged on the base substrate, and adjacent to the plurality of chips; a terminal expansion layer arranged on the base substrate; and a plurality of expansion wires in the terminal expansion layer and configured to electrically connect the chips, wherein an expansion wire configured to electrically connect two chips includes at least a first wire segment and a second wire segment, and the first wire segment is configured to electrically connect a terminal of a chip and a fixed connection portion adjacent to the chip, and the second wire segment is configured to connect two fixed connection portions between the two chips.

First claim

What is claimed is:

1. A semiconductor apparatus, comprising:
a base substrate;
a plurality of chips arranged on the base substrate, wherein each of the plurality of chips comprises a chip main body and a plurality of terminals arranged on the chip main body;
a plurality of fixed connection portions arranged on the base substrate, wherein the plurality of fixed connection portions are arranged adjacent to the plurality of chips, respectively;
a terminal expansion layer arranged on the base substrate, wherein the terminal expansion layer comprises a conductive material; and
a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are configured to electrically connect the plurality of chips,
wherein each of the plurality of expansion wires comprises at least one first wire segment and a second wire segment, and each of the at least one first wire segment is configured to electrically connect a terminal of one of two chips among the plurality of chips and one fixed connection portion of the plurality of fixed connection portions adjacent to the one of the two chips among the plurality of chips, and the second wire segment is configured to connect two fixed connection portions among the plurality of fixed connection portions between the two chips among the plurality of chips,
wherein the plurality of terminals comprise at least a first terminal and a second terminal, and two of the plurality of expansion wires are configured to electrically connect the two chips among the plurality of chips;
wherein one of the two of the plurality of expansion wires is configured to electrically connect respective first terminals of the two chips, and the other of the two of the plurality of expansion wires is configured to electrically connect respective second terminals of the two chips; and
wherein the one of the two of the plurality of expansion wires configured to electrically connect the respective first terminals of the two chips comprises the second wire segment parallel to the second wire segment comprised in the other of the two of the plurality of expansion wires configured to electrically connect the respective second terminals of the two chips, and/or
the one of the two of the plurality of expansion wires configured to electrically connect the respective first terminals of the two chips comprises the second wire segment having a length equal to a length of the second wire segment comprised in the other of the two of the plurality of expansion wires configured to electrically connect the respective second terminals of the two chips.

2. The semiconductor apparatus according to claim 1 , wherein the second wire segment extends in a first direction; and
in two chips among the plurality of chips electrically connected through one of the plurality of expansion wires comprising the second wire segment that extends in the first direction, a relative position of one of the two chips among the plurality of chips in the first direction is different from a relative position of the other one of the two chips among the plurality of chips in the first direction.

3. The semiconductor apparatus according to claim 2 , wherein in two chips among the plurality of chips electrically connected through one of the plurality of expansion wires comprising the second wire segment, at least one of the two chips among the plurality of chips is inclined relative to an extension line of the second wire segment.

4. The semiconductor apparatus according to claim 2 , wherein the at least one first wire segment and the second wire segment adjacent to and electrically connected to the at least one first wire segment have an angle greater than 0° and less than 180°.

5. The semiconductor apparatus according to claim 2 , wherein the plurality of expansion wires comprise a plurality of first wire segments located in a same layer, and
the second wire segment and the at least one first wire segment are located in a same layer or in different layers.

6. The semiconductor apparatus according to claim 1 , wherein in two chips among the plurality of chips electrically connected through one of the plurality of expansion wires comprising the second wire segment, at least one of the two chips among the plurality of chips is inclined relative to an extension line of the second wire segment.

7. The semiconductor apparatus according to claim 6 , wherein in the two chips electrically connected through the one of the plurality of expansion wires comprising the second wire segment, an orientation of one of the two chips relative to the extension line of the second wire segment is different from an orientation of the other one of the two chips relative to the extension line of the second wire segment.

8. The semiconductor apparatus according to claim 1 , wherein the at least one first wire segment and the second wire segment adjacent to and electrically connected to the at least one first wire segment have an angle greater than 0° and less than 180°.

9. The semiconductor apparatus according to claim 8 , wherein one of the plurality of expansion wires comprises two first wire segments and the second wire segment; and
wherein each of the two first wire segments is adjacent to and electrically connected to the second wire segment, an angle between one of the two first wire segments and the second wire segment adjacent thereto and electrically connected thereto is different from an angle between the other one of the two first wire segments and the second wire segment adjacent thereto and electrically connected thereto.

10. The semiconductor apparatus according to claim 1 , wherein one of the two of the plurality of expansion wires configured to electrically connect the two chips comprises a first wire segment in the at least one first wire segment electrically connected to the first terminal of one of the two chips, and the other one of the two of the plurality of expansion wires configured to electrically connect the two chips comprises a first wire segment in the at least one first wire segment electrically connected to the second terminal of the same one of the two chips; and
wherein an angle between the first wire segment electrically connected to the first terminal and the second wire segment adjacent and electrically connected to the first wire segment electrically connected to the first terminal is different from an angle between the first wire segment electrically connected to the second terminal and the second wire segment adjacent and electrically connected to the first wire segment electrically connected to the second terminal.

11. The semiconductor apparatus according to claim 1 , wherein the plurality of expansion wires comprise a plurality of first wire segments located in a same layer, and
the second wire segment and the at least one first wire segment are located in a same layer or in different layers.

12. The semiconductor apparatus according to claim 1 , wherein the plurality of chips are arranged in an array in a first direction and a second direction, and
the at least one first wire segment is inclined relative to the first direction and the second direction.

13. The semiconductor apparatus according to claim 12 , wherein the second wire segment extends in the first direction or in the second direction.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Chenyang
• Li Fuqiang
• Dong Xue
• Wang Meili
• Liang Xuan
• Wang Fei
• Wang Mingxing
• Cao Zhanfeng
• Han Yanling
• Zhao Xinxin

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W70/652

  Cross-sectional shapes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title