Page buffer circuits in three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-12277993-B2
Application number	US-202418420023-A
Country	US
Kind code	B2
Filing date	Jan 23, 2024
Priority date	Jun 29, 2021
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A page buffer circuit of a memory device includes a first sensing branch including a first pre-charge path and a low-voltage latch, and a second sensing branch including a second pre-charge path and a sensing latch. The first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer circuit.

First claim

What is claimed is:

1. A page buffer circuit of a memory device, comprising:
a first sensing branch comprising a first pre-charge path and a low-voltage latch; and
a second sensing branch comprising a second pre-charge path and a sensing latch,
wherein the first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer circuit.

2. The page buffer circuit of claim 1 , wherein the second sensing branch is coupled to the sensing node through a switch.

3. The page buffer circuit of claim 2 , wherein the second pre-charge path is coupled to the sensing node through the switch.

4. The page buffer circuit of claim 2 , wherein the sensing latch is coupled to the sensing node through the switch.

5. The page buffer circuit of claim 1 , wherein a first circuit configuration of the first pre-charge path is the same as a second circuit configuration of the second pre-charge path.

6. The page buffer circuit of claim 1 , wherein
the first pre-charge path further comprises a first bit line voltage supply and selection circuit; and
the second pre-charge path further comprises a second bit line voltage supply and selection circuit.

7. The page buffer circuit of claim 6 , wherein the first bit line voltage supply and selection circuit are coupled to the second bit line voltage supply and selection circuit.

8. The page buffer circuit of claim 1 , further comprising a cache latch coupled to the sensing node.

9. The page buffer circuit of claim 1 , further comprising:
a third sensing branch, wherein the first, the second, and the third sensing branches are parallel coupled to the sensing node of the page buffer circuit.

10. A memory device, comprising:
bit lines; and
page buffers coupled to the bit lines,
wherein one of the page buffers comprises a first sensing branch comprising a first pre-charge path and a low-voltage latch, and a second sensing branch comprising a second pre-charge path and a sensing latch; and
the first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer.

11. The memory device of claim 10 , wherein the second sensing branch is coupled to the sensing node through a switch.

12. The memory device of claim 11 , wherein the second pre-charge path is coupled to the sensing node through the switch.

13. The memory device of claim 11 , wherein the sensing latch is coupled to the sensing node through the switch.

14. The memory device of claim 10 , wherein a first circuit configuration of the first pre-charge path is the same as a second circuit configuration of the second pre-charge path.

15. The memory device of claim 10 , wherein
the first pre-charge path further comprises a first bit line voltage supply and selection circuit; and
the second pre-charge path further comprises a second bit line voltage supply and selection circuit.

16. The memory device of claim 15 , wherein the first bit line voltage supply and selection circuit are coupled to the second bit line voltage supply and selection circuit.

17. The memory device of claim 10 , wherein one of the page buffers further comprises a cache latch coupled to the sensing node.

18. A method for operating a memory device, comprising
performing pre-charge operations, develop operations, and sensing operations respectively, by at least two sensing branch coupled to a sensing node in a page buffer circuit, to at least two bit line segments that are aligned with each other along a bit line direction,
wherein the least two bit line segments are respectively coupled to the at least two sensing branch in the same page buffer circuit.

19. The method of claim 18 , further comprising:
pre-charging, by the page buffer circuit, a first and a second bit line segment of the least two bit line segments during a first period; and
pre-charging, by the page buffer circuit, the sensing node during the first period.

20. The method of claim 19 , further comprising:
adjusting, by the page buffer circuit, potential of the sensing node during a second period after the first period.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Teng
• Wang Yan
• Kuriyama Masao

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title