Nonvolatile memory devices providing reduced data line load

Patent metadata

Field	Value
Publication number	US-10460813-B2
Application number	US-201815900023-A
Country	US
Kind code	B2
Filing date	Feb 20, 2018
Priority date	Mar 22, 2017
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

A nonvolatile memory device according to some embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array;
a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising:
a first high-voltage circuit comprising a first bit line selection circuit connected to the first plurality of bit lines;
a first bit line shut-off circuit connected to the first plurality of bit lines via the first bit line selection circuit; and
a first latch circuit configured to input and output data via a first data line; and

a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising;
a second high-voltage circuit comprising a second bit line selection circuit connected to the second plurality of bit lines;
a second bit line shut-off circuit connected to the second plurality of bit lines via the second bit line selection circuit; and
a second latch circuit configured to input and output data via a second data line,

wherein the first bit line selection circuit and the second bit line selection circuit are on a first region of a main surface of a substrate, the first bit line shut-off circuit and the second bit line shut-off circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on a third region of the main surface of the substrate,
wherein the first region, the second region, and the third region are sequentially arranged on the main surface of the substrate in a direction away from the memory cell array, and
wherein a width of the first data line and a width of the second data line are each greater than a width of each of the first plurality of bit lines and a width of each of the second plurality of bit lines.

2. The nonvolatile memory device of claim 1 , further comprising:
a plurality of layers on the substrate,
wherein the first data line and the second data line are connected to the first latch circuit and the second latch circuit, respectively, on a first layer of the plurality of layers.

3. The nonvolatile memory device of claim 2 , wherein the first plurality of bit lines and the second plurality of bit lines are on the first layer.

4. The nonvolatile memory device of claim 1 ,
wherein the first page buffer further comprises a first discharge circuit that is configured to discharge the first plurality of bit lines, the first discharge circuit being between the first bit line selection circuit and the first latch circuit, and
wherein the second page buffer further comprises a second discharge circuit that is configured to discharge the second plurality of bit lines, the second discharge circuit being between the second bit line selection circuit and the second latch circuit in the direction away from the memory cell array.

5. The nonvolatile memory device of claim 4 ,
wherein the first discharge circuit comprises a first discharge transistor comprising a first discharge transistor gate line,
wherein the second discharge circuit comprises a second discharge transistor comprising a second discharge transistor gate line,
wherein the first bit line selection circuit comprises a first selection transistor comprising a first selection transistor gate line,
wherein the second bit line selection circuit comprises a second selection transistor comprising a second selection transistor gate line, and
wherein a thickness of the first discharge transistor gate line and a thickness of the second discharge transistor gate line are each less than a thickness of the first selection transistor gate line and a thickness of the second selection transistor gate line.

6. The nonvolatile memory device of claim 1 ,
wherein the first latch circuit comprises a first main latch and a first cache latch,
wherein the second latch circuit comprises a second main latch and a second cache latch, and
wherein the first main latch, the first cache latch, the second main latch, and the second cache latch are sequentially arranged on the main surface of the substrate in the direction away from the memory cell array.

7. The nonvolatile memory device of claim 1 ,
wherein the first latch circuit comprises a first data latch and a first cache latch,
wherein the second latch circuit comprises a second data latch and a second cache latch, and
wherein the first data latch, the second data latch, the first cache latch, and the second cache latch are sequentially arranged on the main surface of the substrate in the direction away from the memory cell array.

8. A nonvolatile memory device comprising:
a memory cell array;
a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising a first high-voltage circuit connected to the first plurality of bit lines, a first low-voltage circuit connected to the first plurality of bit lines via the first high-voltage circuit, and a first latch circuit configured to input and output data via a first data line; and
a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising a second high-voltage circuit connected to the second plurality of bit lines, a second low-voltage circuit connected to the second plurality of bit lines via the second high-voltage circuit, and a second latch circuit configured to input and output data via a second data line,
wherein the first high-voltage circuit and the second high-voltage circuit are on a first region of a main surface of a substrate, the first low-voltage circuit and the second low-voltage circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on a third region of the main surface of the substrate,
wherein the first region, the second region, and the third region are sequentially arranged on the main surface of the substrate in a direction away from the memory cell array, and
wherein the first high-voltage circuit and the second high-voltage circuit are configured to receive respective voltages comprising higher ranges than voltages that the first low-voltage circuit and the second low-voltage circuit are configured to receive.

9. The nonvolatile memory device of claim 8 ,
wherein a width of the first data line and a width of the second data line are each greater than a width of each of the first plurality of bit lines and a width of each of the second plurality of bit lines.

10. The nonvolatile memory device of claim 8 ,
wherein the first plurality of bit lines comprise a first bit line of a first bit line group and a second bit line of a second bit line group,
wherein the second plurality of bit lines comprise a third bit line of the first bit line group and a fourth bit line of the second bit line group,
wherein the first page buffer is connected to the first bit line of the first bit line group and the second bit line of the second bit line group, and
wherein the second page buffer is connected to the third bit line of the first bit line group and the fourth bit line of the second bit line group.

11. The nonvolatile memory device of claim 8 ,
wherein the first high-voltage circuit comprises a plurality of selection transistors connected to respective ones of the first plurality of bit lines, and
wherein the first low-voltage circuit comprises a shut-off transistor configured to perform a shut-off operation of at least one of the first plurality of bit lines.

12. The nonvolatile memory device of claim 8 , wherein the first low-voltage circuit comprises a plurality of discharge transistors that are configured to discharge respec

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jeung-Hwan

Classifications

• G11C7/1087 Primary

  Data input latches · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title