Gate driving circuit and manufacturing method therefor, array substrate, and display device

Patent metadata

Field	Value
Publication number	US-12274094-B2
Application number	US-202117801003-A
Country	US
Kind code	B2
Filing date	Oct 12, 2021
Priority date	Nov 27, 2020
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

Provided is a gate driving circuit. The gate driving circuit includes a plurality of first transistors; wherein at least one first target transistor of the plurality of first transistors includes a first light-shielding layer disposed on a side of a base substrate, the first light-shielding layer being made of a conductive material; and a first gate metal layer and a first source/drain metal layer disposed on a side of the first light-shielding layer away from the base substrate; wherein the first light-shielding layer is connected to the first gate metal layer.

First claim

What is claimed is:

1. A gate driving circuit, comprising: a plurality of first transistors; wherein at least one first target transistor of the plurality of first transistors comprises:
a first light-shielding layer disposed on a side of a base substrate, the first light-shielding layer being made of a conductive material;
a first gate metal layer and a first source/drain metal layer disposed on a side of the first light-shielding layer away from the base substrate, wherein the first light-shielding layer is connected to the first gate metal layer;
an active layer and a gate insulating layer, wherein the active layer, the gate insulating layer, the first gate metal layer, and the first source/drain metal layer are sequentially laminated along a direction away from the first light-shielding layer; and
a buffer layer, an interlayer dielectric layer, and a passivation layer; wherein the buffer layer is disposed between the first light-shielding layer and the active layer; the interlayer dielectric layer is disposed between the first source/drain metal layer and the first gate metal layer; and the passivation layer is disposed on a side of the first source/drain metal layer away from the interlayer dielectric layer;
wherein the passivation layer, the buffer layer, and the interlayer dielectric layer are provided with a first via hole therein; the passivation layer and the interlayer dielectric layer are further provided with a second via hole therein; and the at least one first target transistor further comprises: a first connection portion; wherein the first connection portion is connected to the first light-shielding layer through the first via hole, and is connected to the first gate metal layer through the second via hole.

2. The gate driving circuit according to claim 1 , wherein the conductive material is a metal material.

3. The gate driving circuit according to claim 1 , wherein a thickness of the first light-shielding layer is greater than a thickness threshold.

4. The gate driving circuit according to claim 1 , wherein the plurality of first transistors comprise: an input transistor, a reset transistor, a first output transistor, a second output transistor, a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, a fifth pull-down control transistor, a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor; wherein
a gate and a first electrode of the input transistor are connected to an input terminal, and a second electrode of the input transistor is connected to a pull-up node;
a gate of the first output transistor is connected to the pull-up node, a first electrode of the first output transistor is connected to a first clock signal terminal, and a second electrode of the first output transistor is connected to a shift output terminal;
a gate of the second output transistor is connected to the pull-up node, a first electrode of the second output transistor is connected to a second clock signal terminal, and a second electrode of the second output transistor is connected to a driving output terminal;
a gate of the reset transistor is connected to a reset signal terminal, a first electrode of the reset transistor is connected to a first pull-down power supply terminal, and a second electrode of the reset transistor is connected to the pull-up node;
a gate and a first electrode of the first pull-down control transistor are both connected to a pull-down control power supply terminal, and a second electrode of the first pull-down control transistor is connected to a gate of the second pull-down control transistor;
a first electrode of the second pull-down control transistor is connected to the pull-down control power supply terminal, and a second electrode of the second pull-down control transistor is connected to a pull-down node;
a gate of the third pull-down control transistor and a gate of the fourth pull-down control transistor are both connected to the pull-up node, and a first electrode of the third pull-down control transistor and a first electrode of the fourth pull-down control transistor are both connected to the first pull-down power supply terminal, a second electrode of the third pull-down control transistor is connected to the gate of the second pull-down control transistor, and a second electrode of the fourth pull-down control transistor is connected to the pull-down node;
a gate of the fifth pull-down control transistor is connected to a shift output terminal of another cascaded gate driving circuit, a first electrode of the fifth pull-down control transistor is connected to the first pull-down power supply terminal, and a second electrode of the fifth pull-down control transistor is connected to the pull-down node;
a gate of the first pull-down transistor, a gate of the second pull-down transistor and a gate of the third pull-down transistor are all connected to the pull-down node, a first electrode of the first pull-down transistor and a first electrode of the second pull-down transistor are both connected to the first pull-down power supply terminal, a first electrode of the third pull-down transistor is connected to a second pull-down power supply terminal, a second electrode of the first pull-down transistor is connected to the pull-up node, a second electrode of the second pull-down transistor is connected to the shift output terminal, and a second electrode of the third pull-down transistor is connected to the driving output terminal; and
a gate of the fourth pull-down transistor is connected to a shift output terminal of another gate driving circuit, a first electrode of the fourth pull-down transistor is connected to the first pull-down power supply terminal, and a second electrode of the fourth pull-down transistor is connected to the pull-up node.

5. The gate driving circuit according to claim 4 , wherein the gate driving circuit further comprises a storage capacitor, one end of the storage capacitor is connected to the pull-up node, and the other end of the storage capacitor is connected to the driving output terminal.

6. The gate driving circuit according to claim 4 , wherein the at least one first target transistor comprises at least one of: the second output transistor, the second pull-down transistor or the third pull-down transistor.

7. The gate driving circuit according to claim 6 , wherein
the conductive material is a metal material; and a thickness of the first light-shielding layer is greater than a thickness threshold;
the at least one first target transistor further comprises: an active layer and a gate insulating layer; wherein the active layer, the gate insulating layer, the first gate metal layer and the first source/drain metal layer are sequentially laminated along a direction away from the first light-shielding layer;
an orthographic projection of the first light-shielding layer on the base substrate covers an orthographic projection of the active layer on the base substrate;
the at least one first target transistor further comprises: a buffer layer, an interlayer dielectric layer and a passivation layer; wherein the buffer layer is disposed between the first light-shielding layer and the active layer; the interlayer dielectric layer is disposed between the first source/drain metal layer and the first gate metal layer; and the passivation layer is disposed on a side of the first source/drain metal layer away from the interlayer dielectric layer;
the passivation layer, the buffer layer and the interlayer dielectric layer are provided with a first via hole therein; the passivation layer and the interlayer dielectric layer are further provided with a second via

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Su Tongshang
• Cheng Jun
• Zhou Bin
• Zhao Ce
• Wang Qinghe
• Wang Jun
• Yan Liangchen

Classifications

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title