Error correction code decoder, storage controller and storage device

Patent metadata

Field	Value
Publication number	US-12273127-B2
Application number	US-202318218294-A
Country	US
Kind code	B2
Filing date	Jul 5, 2023
Priority date	Dec 5, 2022
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.

First claim

What is claimed is:

1. An error correction code (ECC) decoder comprising:
an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector;
a pre-decoder configured to sequentially receive the first read data by unit of sector, in parallel with the input manager receiving the first read data and configured to generate a respective syndrome of each of the plurality of data units sequentially; and
a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome, by unit of sector,
wherein, the input manager includes a defective sector buffer and is configured to:
in response to the first ECC decoding on a first data unit of the plurality of data units being failed, store the first data unit in the defective sector buffer; and
in response to the first ECC decoding on a second data unit of the plurality of data units being failed, selectively store the second data unit in the defective sector buffer based on an expected error count of each of the first data unit and the second data unit, and

wherein the main decoder is configured to perform a second ECC decoding on a defective data unit stored in the defective sector buffer and receive a second read data from a selected sector corresponding to the defective data unit, from among the plurality of sectors.

2. The ECC decoder of claim 1 , wherein:
each of the plurality of data units corresponds to a hard decision data that is read from each of the plurality of sectors based on a default read voltage; and
the second read data corresponds to a soft decision data that is read from the selected sector based on offset read voltages that have an offset with respect to the default read voltage.

3. The ECC decoder of claim 1 ,
wherein the main decoder is configured to provide a first expected error count associated with the first data unit and a second expected error count associated with the second data unit to the input manager, the first expected error count and the second expected error count being generated during the first ECC decoding on each of the first data unit and the second data unit; and
wherein the input manager further includes a buffer controller configured to selectively update the second data unit in the defective sector buffer based on a comparison of the first expected error count and the second expected error count.

4. The ECC decoder of claim 3 , wherein, in response to the second expected error count being smaller than the first expected error count, the buffer controller is configured to update the second data unit in the defective sector buffer.

5. The ECC decoder of claim 3 , wherein, in response to the second expected error count being equal to or greater than the first expected error count, the buffer controller is configured to maintain the first data unit in the defective sector buffer.

6. The ECC decoder of claim 3 , wherein the input manager further comprises:
a first sector buffer configured to store the plurality of data units sequentially;
a second sector buffer configured to store the second read data,
wherein the buffer controller comprises:
a register configured to store the first expected error count and the second expected error count;
a comparator configured to generate a comparison signal by comparing the first expected error count and the second expected error count stored in the register; and
a control logic connected to the defective sector buffer and the first sector buffer, and configured to control an updating operation of the defective sector buffer based on the comparison signal.

7. The ECC decoder of claim 3 , further comprising:
an output manager connected to the main decoder,
wherein the input manager further comprises:
a buffer controller configured to selectively update the second data unit in the defective sector buffer based on a comparison of the first expected error count and the second expected error count;
a first sector buffer configured to store the plurality of data units sequentially; and
a second sector buffer configured to store the second read data,

wherein the pre-decoder comprises:
a syndrome calculator configured to generate syndromes of the plurality of data units sequentially; and
a syndrome buffer configured to store a first syndrome associated with the first data unit and configured to selectively update a second syndrome associated with the second data unit in response to the second data unit being selectively updated in the defective sector buffer.

8. The ECC decoder of claim 1 ,
wherein the main decoder is configured to provide a first expected error count associated with the first data unit and a second expected error count associated with the second data unit to the input manager, the first expected error count and the second expected error count being generated during the first ECC decoding on each of the first data unit and the second data unit; and
wherein the pre-decoder comprises:
a syndrome calculator configured to generate the syndrome of each of the plurality of data units sequentially; and
a syndrome buffer connected to the syndrome calculator.

9. The ECC decoder of claim 8 , wherein the syndrome buffer is configured to:
store a first syndrome associated with the first data unit; and
selectively update a second syndrome associated with the second data unit in response to the second data unit being selectively updated in the defective sector buffer.

10. The ECC decoder of claim 9 , wherein the main decoder is configured to:
generate a first syndrome weight based on the first syndrome associated with the first data unit;
generate a second syndrome weight based on the second syndrome associated with the second data unit; and
provide the input manager with the first syndrome weight and the second syndrome weight as the first expected error count and the second expected error count, respectively, and
wherein each of the first syndrome weight and the second syndrome weight indicates a number of bits having a first logic level in each of the first syndrome and the second syndrome in a plurality of iterations of the first ECC decoding on each of the first data unit and the second data unit.

11. The ECC decoder of claim 1 ,
wherein the main decoder is configured to provide a first expected error count associated with the first data unit and a second expected error count associated with the second data unit to the input manager, the first expected error count and the second expected error count being generated during the first ECC decoding on each of the first data unit and the second data unit; and
wherein the main decoder comprises:
log likelihood ratio (LLR) mapper configured to output LLR data by mapping LLR values to the plurality of data units in the first ECC decoding and mapping the LLR values to the second read data in the second ECC decoding;
a variable node processor including variable nodes, the variable node processor configured to store the LLR data to provide the LLR data to a first switch network as a variable node message;
a check node processor connected to the first switch network and including check nodes, the check node processor configured to process a value of each of the variable nodes with respect to each of the check nodes, by referring to the variable node message and the syndromes, to provide the processed value to a second switch network as a check node message.

12. The ECC decoder of claim 11 , wherein the variable node processor is configured to:
update the values of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Jaehun
• Seo Mankeun
• Son Hongrak
• Jun Bohwan

Classifications

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• H03M13/151

  using error location or error correction polynomials · CPC title