Operating method of error correction code decoder and memory controller including the error correction code decoder

Patent metadata

Field	Value
Publication number	US-9602134-B2
Application number	US-201414314774-A
Country	US
Kind code	B2
Filing date	Jun 25, 2014
Priority date	Aug 8, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An operating method of an ECC decoder includes receiving first chunk data and second chunk data from a nonvolatile memory device, the second chunk data subsequent to the first chunk data, performing error correction on the first chunk data, determining if the first chunk data includes an uncorrectable error bit and determining not to perform error correction on the second chunk data in response to the first chunk data including the uncorrectable error bit.

First claim

What is claimed is:

1. An operating method of an error correction code (ECC) decoder which uses a low density parity check (LDPC) code, the operating method comprising:
reading first chunk data of hard-decision data and second chunk data of the hard-decision data from a nonvolatile memory device using a read voltage, the second chunk data received subsequent to the first chunk data;
performing error correction on the first chunk data;
determining if the first chunk data includes an uncorrectable error bit;
determining not to perform error correction on the second chunk data if the first chunk data is determined to include the uncorrectable error bit;
obtaining third chunk data of soft-decision data and fourth chunk data of the soft-decision data in response to the hard-decision data including the uncorrectable error bit, the fourth chunk data obtained subsequent to the third chunk data;
determining if the third chunk data includes the uncorrectable error bit;
determining not to perform error correction on the fourth chunk data if the third chunk data is determined to include the uncorrectable error bit;
adjusting the read voltage;
reading fifth chunk data of the hard-decision data and sixth chunk data of the hard-decision data from the nonvolatile memory device using the adjusted read voltage, the fifth chunk data of the hard-decision data corresponding to the first chunk data of the hard-decision data and the sixth chunk data of the hard-decision data corresponding to the second chunk data of the hard-decision data;
performing error correction on the fifth chunk data;
determining if the fifth chunk data includes the uncorrectable error bit; and
determining not to perform error correction on the sixth chunk data if the fifth chunk data is determined to include the uncorrectable error bit.

2. The operating method of claim 1 , wherein the first chunk data and the second chunk data are in a single page.

3. The operating method of claim 1 , wherein the first chunk data is a unit of error correction.

4. The operating method of claim 1 , further comprising:
storing the first chunk data and the second chunk data in an input buffer.

5. The operating method of claim 1 , further comprising:
providing an uncorrectable error signal to a microprocessor in response to the third chunk data including the uncorrectable error bit.

6. The operating method of claim 1 , further comprising:
providing an error correction stop signal to a microprocessor in response to the third chunk data including the uncorrectable error bit, the error correction stop signal for terminating error correction for the fourth chunk data.

7. The operating method of claim 1 , wherein the first chunk data and the second chunk data are in a single page, and the operating method further comprises:
terminating error correction of the hard-decision data for the single page in response to the first chunk data including the uncorrectable error bit.

8. The operating method of claim 1 , wherein the nonvolatile memory device and the ECC decoder have bus interfaces with different processing speeds.

9. The operating method of claim 1 , further comprising:
storing address information and data size information of the first chunk data and the second chunk data in a queue.

10. A method of operating a nonvolatile memory system, the method comprising:
receiving at least one page of data, the at least one page of data including a plurality of chunks to be decoded;
decoding a selected chunk of the plurality of chunks, the selected chunk including at least one error;
determining if the at least one error is correctable, the determining whether the at least one error is correctable includes,
obtaining first hard-decision information for the selected chunk,
determining if the at least one error is correctable based on the first hard-decision information,
determining not to perform error correction on subsequent chunks of the page if the at least one error is determined to be uncorrectable based on the first hard-decision information,
obtaining first soft-decision information for the selected chunk if the least one error is not correctable based on the first hard-decision information,
determining if the at least one error is correctable based on the first soft-decision information,
determining not to perform error correction on subsequent chunks of the page if the at least one error is determined to be uncorrectable based on the first soft-decision information,
adjusting a read voltage if the at least one error is not correctable based on the first soft-decision information,
obtaining second hard-decision information for the selected chunk using the adjusted read voltage,
determining if the at least one error is correctable based on the second hard-decision information,
determining not to perform error correction on subsequent chunks of the page if the at least one error is determined to be uncorrectable based on the second hard-decision information,
obtaining second soft-decision information for the selected chunk if the at least one error is not correctable based on the second hard-decision information, and
determining if the at least one error is correctable based on the second soft-decision information, and

determining not to perform error correction on subsequent chunks of the page if the at least one error is determined to be uncorrectable based on the second soft-decision information.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyun-Sik
• Cho Young-Jin

Classifications

• G11C2029/0411

  Online error correction · CPC title

• H03M13/1128 Primary

  Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations · CPC title

• H03M13/3738

  with judging correct decoding · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title