Ball bond impedance matching

Patent metadata

Field	Value
Publication number	US-12266629-B2
Application number	US-202117169098-A
Country	US
Kind code	B2
Filing date	Feb 5, 2021
Priority date	Feb 5, 2021
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Methods and apparatus for providing an interconnection including a stack of wirebond balls having a selected impedance. The wirebond balls may have a size, which may comprise a radius, configured for the selected impedance. The stack may comprise a number of wirebond balls configured for the selected impedance and/or may comprise a material selected for the selected impedance. In embodiments, the selected impedance is primarily resistive (e.g., 50 Ohms), such that the overall reactance is minimized.

First claim

What is claimed is:

1. A method of forming an interconnection having a selected impedance, comprising:
providing a board having a first conductive layer, a first dielectric layer having a first hole in the first dielectric layer that exposes a portion of the first conductive layer, and a conductive trace on a top surface of the first dielectric layer;
selecting a number of balls in a ball stack to achieve the selected impedance, wherein the number of balls is at least two;
determining a radius of the balls to achieve desired capacitive and inductance characteristics of the selected impedance, wherein all of the balls have the same determined radius; and
using wire bonding equipment to melt wire to form the number of balls with the same determined radius on top of each other on the exposed portion of the first conductive layer in the first hole and bonded to each other with the top of the ball stack level with the top surface of the first dielectric layer and then to form a single wirebond interconnection from the top of the ball stack to the conductive trace.

2. The method according to claim 1 , wherein the selected impedance is primarily resistive such that the selected impedance minimizes reactance.

3. The method according to claim 1 , wherein the ball stack and the single wirebond interconnection connects an integrated circuit and a circuit card.

4. The method according to claim 1 , wherein the selected impedance is 50 Ohms.

5. The method according to claim 1 , wherein the radius of the wirebond balls ranges from 0.5 mil to 15 mil.

6. The method according to claim 1 , wherein the ball stack has a height ranging from 2 mil to 90 mil.

7. The method according to claim 1 , wherein the ball stack does not contain solder.

8. The method according to claim 1 , wherein the wire is doped.

9. The method according to claim 1 , wherein the radius of the balls is determined to increase a capacitance of the ball stack and canceling cancel out an inductance of the single wirebond interconnection.

10. A method of forming an interconnection having a selected impedance, comprising:
providing a board having a first conductive layer, a first dielectric layer having a first hole in the first dielectric layer that exposes a portion of the first conductive layer, and a conductive trace on a top surface of the first dielectric layer;
using wire bonding equipment to melt wire to form a plurality of balls with a same determined radius on top of each other on the exposed portion of the first conductive layer in the first hole and bonded to each other to form a ball stack with the top of the ball stack level with the top surface of the first dielectric layer; and then
using the wire bonding equipment to form a single wirebond interconnection from the top of the ball stack to the conductive trace.

11. The method of claim 10 , wherein the number of balls achieves the selected impedance for the ball stack and the radius of the balls achieves desired capacitive and inductance characteristics for the entire ball stack.

12. The method of claim 10 , wherein the selected impedance is primarily resistive, wherein the radius of the plurality of balls is determined to minimize reactance.

13. A method of forming an interconnect system having a selected impedance, comprising:
providing a board having a first conductive layer, a first dielectric layer, a trace on a top surface of the first dielectric layer, a ground pad that forms an arc on the top surface of the first dielectric layer, a first hole in the first dielectric layer positioned at a center of the arc that exposes a portion of the first conductive layer, and a plurality of second holes in the first dielectric layer spaced apart and positioned between the first hole and the arc that expose portions of the first conductive layer,
selecting a number of balls and a radius of the balls to form a ball stack whose height equals a depth of the first hole and the second holes with the number of balls determining the selected impedance and the radius of the balls achieving desired capacitive and inductance characteristics of the selected impedance for the ball stack,
using wire bonding equipment to melt wire to form
a first ball stack in the first hole with the top surface of the first ball stack level with the top surface of the first dielectric layer;
a first wirebond interconnection from the top of the first ball stack to the conductive trace;
a plurality of second ball stacks in the plurality of second holes with the top surfaces of the second ball stacks level with the top surface of the first dielectric layer; and
a plurality of second wirebond interconnections from the tops of the respective plurality of second ball stacks to the ground pad at positions opposite each of the second ball stacks.

Assignees

• Raytheon Co

Inventors

• Boyle Patrick E
• Benedict James E
• Klek Erika
• Pevzner Mikhail

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07511

  Treating the bonding area before connecting, e.g. by applying flux or cleaning · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W72/01551

  Changing the shapes of bond wires · CPC title

• H10W72/075

  of bond wires · CPC title