Integrated circuit structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-12266602-B2
Application number	US-202217572160-A
Country	US
Kind code	B2
Filing date	Jan 10, 2022
Priority date	Jul 16, 2021
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

A method includes forming an interlayer dielectric (ILD) layer over a transistor; forming a first inter-metal dielectric (IMD) layer over the ILD layer; etching a via opening extending through the first IMD layer; forming a first 2-D material layer lining along sides and a bottom of the via opening; depositing a first metal in the via opening and over the first 2-D material layer; performing a chemical mechanism polishing (CMP) process to the first metal until the first IMD layer is exposed; forming a second IMD layer over the first IMD layer; etching a trench in the second IMD layer; forming a second 2-D material layer lining along sides and a bottom of the trench; and depositing a second metal over the second 2-D material layer at a temperature lower than a temperature of depositing the first metal over the first 2-D material layer.

First claim

What is claimed is:

1. A method, comprising:
forming a transistor over a substrate;
forming an interlayer dielectric (ILD) layer over the transistor;
forming a first inter-metal dielectric (IMD) layer over the ILD layer;
etching a via opening extending through the first IMD layer;
forming a first 2-D material layer lining along sides and a bottom of the via opening;
depositing a first metal in the via opening and over the first 2-D material layer;
performing a chemical mechanism polishing (CMP) process to the first metal until the first IMD layer is exposed;
forming a second IMD layer over the first IMD layer;
etching a trench in the second IMD layer;
forming a second 2-D material layer lining along sides and a bottom of the trench; and
depositing a second metal over the second 2-D material layer at a temperature lower than a temperature of depositing the first metal over the first 2-D material layer.

2. The method of claim 1 , wherein the first 2-D material layer is deposited on a surface of the first IMD layer.

3. The method of claim 1 , wherein during depositing the first metal, a temperature increases from a first temperature to a second temperature higher than the first temperature, and then decreases from the second temperature back to the first temperature.

4. The method of claim 1 , further comprising performing an annealing process after depositing the first metal.

5. The method of claim 1 , wherein a grain size of the first metal is larger than a grain size of the second metal.

6. The method of claim 1 , wherein the first metal has more grain clusters than the second metal.

7. A method, comprising:
forming a transistor over a substrate;
forming a first inter-metal dielectric (IMD) layer over the transistor;
forming a first 2-D material layer in the first IMD layer;
forming a metal via in the first IMD layer and over the first 2-D material layer;
forming a second IMD layer over the metal via;
forming a second 2-D material layer in the second IMD layer, wherein the second 2-D material layer spans across the metal via and the first 2-D material layer; and
forming a metal line in the second IMD layer and over the second 2-D material layer, wherein the metal via has more grain clusters than the metal line.

8. The method of claim 7 , wherein top ends of the first 2-D material layer are in contact with a bottom surface the second 2-D material layer.

9. The method of claim 7 , wherein the second 2-D material layer is in contact with a top surface of the metal via.

10. The method of claim 7 , wherein the metal via and the metal line have a single-crystal structure.

11. The method of claim 7 , further comprising forming a gate contact over a gate of the transistor and a third 2-D material layer cupping an underside of the gate contact.

12. The method of claim 7 , further comprising forming a source/drain contact electrically connected with a source/drain region of the transistor and a third 2-D material layer cupping an underside of the source/drain contact.

13. The method of claim 7 , wherein a grain size of the metal via is larger than a grain size of the metal line.

14. The method of claim 7 , wherein the first 2-D material layer is made of a single-element metal or transition metal dichalcogenide.

15. A method, comprising:
forming a transistor over a substrate;
forming a first IMD layer over the transistor;
forming a first barrier layer in the first IMD layer and electrically connected to the transistor;
forming a metal via in the first IMD layer and over the first barrier layer;
forming a second IMD layer over the first IMD layer;
forming a second barrier layer in the second IMD and over the metal via; and
forming a metal line in the second IMD layer and over the second barrier layer, wherein a grain size of the metal via is larger than a grain size of the metal line.

16. The method of claim 15 , wherein the first barrier layer and the second barrier layer are made of 2-D materials.

17. The method of claim 15 , wherein the metal via has more grain clusters than the metal line.

18. The method of claim 15 , further comprising:
forming an interlayer dielectric (ILD) layer over the transistor;
forming a third barrier layer in the ILD layer and electrically connected with a gate structure of the transistor; and
forming a gate contact in the ILD layer and over the third barrier layer.

19. The method of claim 18 , wherein the gate contact has a top surface in contact with the first barrier layer.

20. The method of claim 18 , wherein the third barrier layer is made of a 2-D material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Lin Shih-Yen
• Zhang yu-wei
• Chen Kuan-Chao
• Lee Si-Chen
• Chen Chi

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/033 Primary

  in openings in dielectrics · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title